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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v1 0/9] Enable QUPs and Serial on SA8255p Qualcomm platforms Date: Thu, 10 Apr 2025 23:10:01 +0530 Message-ID: <20250410174010.31588-1-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: l-yVG0K-HDBeKpnBigH7BABoNXxFGyVK X-Proofpoint-ORIG-GUID: l-yVG0K-HDBeKpnBigH7BABoNXxFGyVK X-Authority-Analysis: v=2.4 cv=MpRS63ae c=1 sm=1 tr=0 ts=67f80294 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=pBcTSFWc41ZEPE-p5JgA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_05,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1011 priorityscore=1501 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 phishscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100127 The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The device drivers request resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages UART baud rates, with each baud rate represented by a performance level. Drivers use the dev_pm_opp_set_level() API to request the desired baud rate by specifying the performance level. The QUP drivers are SCMI clients, with clocks, interconnects, pinctrl and power-domains abstracted by a SCMI server. Nikunj Kela (3): opp: add new helper API dev_pm_opp_set_level() dt-bindings: serial: describe SA8255p dt-bindings: qcom: geni-se: describe SA8255p Praveen Talari (6): soc: qcom: geni-se: Enable QUPs on SA8255p Qualcomm platforms serial: qcom-geni: move resource initialization to separate functions serial: qcom-geni: move resource control logic to separate functions serial: qcom-geni: move clock-rate logic to separate function serial: qcom-geni: Enable PM runtime for serial driver serial: qcom-geni: Enable Serial on SA8255p Qualcomm platforms .../serial/qcom,sa8255p-geni-uart.yaml | 59 +++ .../soc/qcom/qcom,sa8255p-geni-se-qup.yaml | 100 +++++ drivers/opp/core.c | 22 ++ drivers/soc/qcom/qcom-geni-se.c | 78 ++-- drivers/tty/serial/qcom_geni_serial.c | 345 ++++++++++++++---- include/linux/pm_opp.h | 6 + 6 files changed, 512 insertions(+), 98 deletions(-) create mode 100644 Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml