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[65.128.205.244]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4e5e32a342asm1426777173.89.2024.12.16.13.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 13:42:55 -0800 (PST) From: Shimrra Shai To: linux-kernel@vger.kernel.org Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, heiko@sntech.de, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, robh@kernel.org, Shimrra Shai Subject: [PATCH v4 0/2] arm64: dts: rockchip: Add Firefly ITX-3588J Board Date: Mon, 16 Dec 2024 15:41:50 -0600 Message-ID: <20241216214152.58387-1-shimrrashai@gmail.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Draft 4 for the device trees for this board. I hope this one finally addresses all outstanding style and organization issues. Note that the technical functionality limitations from the preceding versions remain. Changes since draft 3: * Removed the rockchip-pca9555.h header and used the pin numbers directly in the .dts. * Removed the display-subsystem node in the .dts. No other board seems to have one like the one that was there and it was causing warnings. * Removed extraneous property "rk806_dvs1_pwrdn" on the PMIC subnode on SPI2. * Removed an extraneous property "rockchip,skip-scan-in-resume" on the PCIe node pcie2x1l0. Shimrra --- Shimrra Shai (2): dt-bindings: arm: rockchip: Add Firefly ITX-3588J board arm64: dts: rockchip: add DTs for Firefly ITX-3588J and its Core-3588J SoM .../devicetree/bindings/arm/rockchip.yaml | 7 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3588-firefly-core-3588j.dtsi | 447 +++++++++++ .../dts/rockchip/rk3588-firefly-itx-3588j.dts | 705 ++++++++++++++++++ 4 files changed, 1160 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts