mbox series

[V2,0/3] arm64: dts: qcom: x1e80100: Enable bwmon support

Message ID 20240618154306.279637-1-quic_sibis@quicinc.com
Headers show
Series arm64: dts: qcom: x1e80100: Enable bwmon support | expand

Message

Sibi Sankar June 18, 2024, 3:43 p.m. UTC
This patch series enables bwmon support on X1E80100 SoCs.

V2:
* Allow for opp-tables to be optional on X1E cpu-bwmon instances. [Konrad]
* Drop Rb from Krzysztof due to more bindings changes.
* Use explicit request/free irq and add comments regarding the race
  introduced when adding the IRQF_SHARED flag. [Krzysztof/Dmitry]
* Use consistent numbering of the opps across instances. [Shiv]
* Use ICC_TAG_ACTIVE_ONLY instead of magic numbers. [Konrad]
* Drop fastrpc enablement patch. [Bjorn]

tag: next-20240617
base-commit: 76db4c64526c5e8ba0f56ad3d890dce8f9b00bbc

Sibi Sankar (3):
  dt-bindings: interconnect: qcom,msm8998-bwmon: Add X1E80100 BWMON
    instances
  soc: qcom: icc-bwmon: Allow for interrupts to be shared across
    instances
  arm64: dts: qcom: x1e80100: Add BWMONs

 .../interconnect/qcom,msm8998-bwmon.yaml      |  14 +-
 arch/arm64/boot/dts/qcom/x1e80100.dtsi        | 120 ++++++++++++++++++
 drivers/soc/qcom/icc-bwmon.c                  |  14 +-
 3 files changed, 144 insertions(+), 4 deletions(-)

Comments

Konrad Dybcio June 18, 2024, 4:02 p.m. UTC | #1
On 6/18/24 17:43, Sibi Sankar wrote:
> Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4
> instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR
> path. Also make the opp-table optional for the X1E cpu-bwmon instances,
> since they use the same opp-table between them.
> 
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---

I think we can just drop the opp-table child node from required altogether,
bindings shouldn't care about where the OPP table (which is referenced in
the operating-points-v2 property) comes from

Konrad
Konrad Dybcio June 18, 2024, 7:33 p.m. UTC | #2
On 6/18/24 17:43, Sibi Sankar wrote:
> Add the CPU and LLCC BWMONs on X1E80100 SoCs.
> 
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---

If you're going to resend, please add a comment like:

/* CPU0-3 */

above the respective monitor nodes

Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
Krzysztof Kozlowski June 21, 2024, 6:44 a.m. UTC | #3
On 18/06/2024 18:02, Konrad Dybcio wrote:
> 
> 
> On 6/18/24 17:43, Sibi Sankar wrote:
>> Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4
>> instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR
>> path. Also make the opp-table optional for the X1E cpu-bwmon instances,
>> since they use the same opp-table between them.
>>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>> ---
> 
> I think we can just drop the opp-table child node from required altogether,
> bindings shouldn't care about where the OPP table (which is referenced in
> the operating-points-v2 property) comes from

I agree.

Best regards,
Krzysztof