From patchwork Tue Apr 16 15:37:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 789674 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FD5842A89; Tue, 16 Apr 2024 15:38:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713281891; cv=none; b=RG4zmboFAAM4q/CLBtxmQnXN+cdTiXJ+rjg1rvtqjNAP9vctpXrGGeLUbQRWxjFnewKq/eYs6PG9bn8dtTaKqonS0z6aoriAu7yjVTlg+lBx/yi5NJqcUub6cBPmf8o5I9NmsFIUORALHhLvu66mvT7O6hgX1QdCSHr5b04TBhM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713281891; c=relaxed/simple; bh=u6Z1DEbl0qxU+nlJwpAZ3PPcKHfeSP3iPuCT/kByKmA=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=eIuNQAilKUjSbfNMQVEKmjjbI0zvCokg+MSvAeQhJ1tzqoVlyFIFR7bFwjJADoAcN18xZqXEufLQkqdPCe1h7k8b7nQEbx9Xtl1ofPf1OxDf84IfIbyJGMdrvJhZjsLVABhgUyN839qDq+0Ot/FeSNI+cBZ0NqgCMrNaV5BUPQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=tJ7zAhJy; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="tJ7zAhJy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1713281888; bh=u6Z1DEbl0qxU+nlJwpAZ3PPcKHfeSP3iPuCT/kByKmA=; h=From:To:Cc:Subject:Date:From; b=tJ7zAhJyNIpuLrKAEYB2NkV5PdhWvv0IYxmXLIM7OY+pSCgp66qX3t0DxHpeVnzwD MJfdxJMq3YqBWolopIyvdgUKfAGpeezzqxlGjayxPLgR69/UcnE+l7SA9GJzjuD7/1 GbRVi8LXZNWNtYv/MkwkOSfqfDrdolVQFsLUXoI5seQNvQKkD4+Kxz9O8Bvuou8Gfd EH6C89O5SVZ3v00SXsTN+ZVKun9+3NQSCwzIAM3anSHBEObGgykSP3lH7j92AkjE5K OFQtcx8xFXivGTdYadZIaO+hPqw+bfOjK+8z/05tGv9+N2E/nM14JyikP2pXvpOGju zL6YZ8QixZRFA== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 45CA537804B2; Tue, 16 Apr 2024 15:38:07 +0000 (UTC) From: AngeloGioacchino Del Regno To: djakov@kernel.org Cc: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, lgirdwood@gmail.com, broonie@kernel.org, keescook@chromium.org, gustavoars@kernel.org, henryc.chen@mediatek.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, amergnat@baylibre.com Subject: [PATCH v1 0/6] MediaTek DVFSRC Bus Bandwidth and Regulator knobs Date: Tue, 16 Apr 2024 17:37:59 +0200 Message-ID: <20240416153805.431118-1-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This series adds support for the MediaTek Dynamic Voltage and Frequency Scaling Resource Controller (DVFSRC), found on many MediaTek SoCs. This hardware collects requests from both software and the various remote processors embededd into the SoC, and decides about a minimum operating voltage and a minimum DRAM frequency to fulfill those requests, in an effort to provide the best achievable performance per watt. Such hardware IP is capable of transparently performing direct register R/W on all of the DVFSRC-controlled regulators and SoC bandwidth knobs. Summarizing how the DVFSRC works for Interconnect: ICC provider ICC Nodes ---- ---- _________ |CPU | |--- |VPU | _____ | |----- ---- | ---- | |->| DRAM | ---- | ---- |DRAM |->|scheduler|----- |GPU | |--- |DISP| | |->| (EMI) | ---- | ---- |_____|->|_________|---. ----- | ---- /|\ `-|MMSYS|--|--- |VDEC| | ----- | ---- | | ---- | change DRAM freq |--- |VENC| -------- | ---- SMC --> | DVFSRC | | ---- -------- |--- |IMG | | ---- | ---- |--- |CAM | ---- ...and for regulators, it's simply... SMC -> DVFSRC -> Regulator voltage decider -> (vreg) Registers R/W Please note that this series is based on an old (abandoned) series from MediaTek [1], and reuses some parts of the code found in that. Besides, included in this series, there's also a refactoring of the mtk-dvfsrc-regulator driver, which never got compiled at all, and would not build anyway because of missing headers and typos: that commit did not get any Fixes tag because, well, backporting makes no sense at all as the DVFSRC support - which is critical for that driver to work - is introduced with *this series*! :-) P.S.: The DVFSRC regulator is a requirement for the MediaTek UFSHCI controller's crypto boost feature, which is already upstream but lacking the actual regulator to work....... :-) [1]: https://lore.kernel.org/all/20210812085846.2628-1-dawei.chien@mediatek.com/ Cheers! AngeloGioacchino Del Regno (6): dt-bindings: soc: mediatek: Add DVFSRC bindings for MT8183 and MT8195 dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings dt-bindings: regulator: Add bindings for MediaTek DVFSRC Regulators soc: mediatek: Add MediaTek DVFS Resource Collector (DVFSRC) driver regulator: mtk-dvfsrc-regulator: Refactor and add MT8192/MT8195 vregs interconnect: mediatek: Add MediaTek MT8183/8195 EMI Interconnect driver .../interconnect/mediatek,mt8183-emi.yaml | 76 +++ .../mediatek,mt6873-dvfsrc-regulator.yaml | 71 +++ .../soc/mediatek/mediatek,mt8183-dvfsrc.yaml | 57 ++ drivers/interconnect/Kconfig | 1 + drivers/interconnect/Makefile | 1 + drivers/interconnect/mediatek/Kconfig | 32 + drivers/interconnect/mediatek/Makefile | 5 + drivers/interconnect/mediatek/icc-emi.c | 153 +++++ drivers/interconnect/mediatek/icc-emi.h | 40 ++ drivers/interconnect/mediatek/mt8183.c | 143 +++++ drivers/interconnect/mediatek/mt8195.c | 339 +++++++++++ drivers/regulator/mtk-dvfsrc-regulator.c | 242 ++++---- drivers/soc/mediatek/Kconfig | 11 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-dvfsrc.c | 551 ++++++++++++++++++ .../interconnect/mediatek,mt8183.h | 23 + .../interconnect/mediatek,mt8195.h | 44 ++ include/linux/soc/mediatek/dvfsrc.h | 36 ++ include/linux/soc/mediatek/mtk_sip_svc.h | 3 + 19 files changed, 1699 insertions(+), 130 deletions(-) create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml create mode 100644 drivers/interconnect/mediatek/Kconfig create mode 100644 drivers/interconnect/mediatek/Makefile create mode 100644 drivers/interconnect/mediatek/icc-emi.c create mode 100644 drivers/interconnect/mediatek/icc-emi.h create mode 100644 drivers/interconnect/mediatek/mt8183.c create mode 100644 drivers/interconnect/mediatek/mt8195.c create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c create mode 100644 include/dt-bindings/interconnect/mediatek,mt8183.h create mode 100644 include/dt-bindings/interconnect/mediatek,mt8195.h create mode 100644 include/linux/soc/mediatek/dvfsrc.h