| Message ID | 20230821-topic-sm8x50-upstream-cpufreq-4-domains-v1-0-2d4d9fc828d8@linaro.org |
|---|---|
| Headers | show |
| Series | qcom-cpufreq-hw: add support for 4 freq domains | expand |
On Mon, Aug 21, 2023 at 09:39:13AM +0200, Neil Armstrong wrote: > On new platforms, a 4th frequency domain is used, document it. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> - Mani > --- > Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > index a6b3bb8fdf33..c1d225fcf2d5 100644 > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > @@ -49,6 +49,7 @@ properties: > - description: Frequency domain 0 register region > - description: Frequency domain 1 register region > - description: Frequency domain 2 register region > + - description: Frequency domain 3 register region > > reg-names: > minItems: 1 > @@ -56,6 +57,7 @@ properties: > - const: freq-domain0 > - const: freq-domain1 > - const: freq-domain2 > + - const: freq-domain3 > > clocks: > items: > @@ -69,7 +71,7 @@ properties: > > interrupts: > minItems: 1 > - maxItems: 3 > + maxItems: 4 > > interrupt-names: > minItems: 1 > @@ -77,6 +79,7 @@ properties: > - const: dcvsh-irq-0 > - const: dcvsh-irq-1 > - const: dcvsh-irq-2 > + - const: dcvsh-irq-3 > > '#freq-domain-cells': > const: 1 > > -- > 2.34.1 >
On Mon, Aug 21, 2023 at 09:39:13AM +0200, Neil Armstrong wrote: > On new platforms, a 4th frequency domain is used, document it. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > index a6b3bb8fdf33..c1d225fcf2d5 100644 > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > @@ -49,6 +49,7 @@ properties: > - description: Frequency domain 0 register region > - description: Frequency domain 1 register region > - description: Frequency domain 2 register region > + - description: Frequency domain 3 register region > > reg-names: > minItems: 1 > @@ -56,6 +57,7 @@ properties: > - const: freq-domain0 > - const: freq-domain1 > - const: freq-domain2 > + - const: freq-domain3 > > clocks: > items: > @@ -69,7 +71,7 @@ properties: > > interrupts: > minItems: 1 > - maxItems: 3 > + maxItems: 4 > > interrupt-names: > minItems: 1 > @@ -77,6 +79,7 @@ properties: > - const: dcvsh-irq-0 > - const: dcvsh-irq-1 > - const: dcvsh-irq-2 > + - const: dcvsh-irq-3 Truly useless names with foo<index>... Acked-by: Rob Herring <robh@kernel.org>
New platforms can have up to to 4 frequency domains, Document and add support for this. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Neil Armstrong (2): dt-bindings: cpufreq: qcom-hw: add a 4th frequency domain cpufreq: qcom-cpufreq-hw: add support for 4 freq domains Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 5 ++++- drivers/cpufreq/qcom-cpufreq-hw.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) --- base-commit: 47d9bb711707d15b19fad18c8e2b4b027a264a3a change-id: 20230821-topic-sm8x50-upstream-cpufreq-4-domains-2ca50ff2cce2 Best regards,