From patchwork Tue Mar 23 13:56:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Lu X-Patchwork-Id: 407250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EE06C433E3 for ; Tue, 23 Mar 2021 13:57:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 11D32619C1 for ; Tue, 23 Mar 2021 13:57:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231741AbhCWN5Q (ORCPT ); Tue, 23 Mar 2021 09:57:16 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34751 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231602AbhCWN5E (ORCPT ); Tue, 23 Mar 2021 09:57:04 -0400 X-UUID: 831725d4f06a420883594fa86afc2c17-20210323 X-UUID: 831725d4f06a420883594fa86afc2c17-20210323 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 597238201; Tue, 23 Mar 2021 21:57:01 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 21:56:58 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Mar 2021 21:56:58 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd , Philipp Zabel CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Nishanth Menon , Roger Lu , , , , , , Subject: [PATCH v13 0/7] soc: mediatek: SVS: introduce MTK SVS Date: Tue, 23 Mar 2021 21:56:50 +0800 Message-ID: <20210323135657.2701-1-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: A33E67F89CD86AA5EB5C20A89A9B6C49CB4E1286C37074145C82D3EADA8A33B72000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org 1. SVS driver uses OPP adjust event in [1] to update OPP table voltage part. 2. SVS driver gets thermal/GPU device by node [2][3] and CPU device by get_cpu_device(). After retrieving subsys device, SVS driver does device_link_add() to make sure probe/suspend callback priority. 3. SVS dts refers to reset controller [4] to help reset SVS HW. #mt8183 SVS related patches [1] https://patchwork.kernel.org/patch/11193513/ [2] https://patchwork.kernel.org/project/linux-mediatek/patch/20201013102358.22588-2-michael.kao@mediatek.com/ [3] https://patchwork.kernel.org/project/linux-mediatek/patch/20200306041345.259332-3-drinkcat@chromium.org/ #mt8192 SVS related patches [1] https://patchwork.kernel.org/patch/11193513/ [2] https://patchwork.kernel.org/project/linux-mediatek/patch/20201223074944.2061-1-michael.kao@mediatek.com/ [3] https://lore.kernel.org/patchwork/patch/1360551/ [4] https://patchwork.kernel.org/project/linux-mediatek/patch/20200817030324.5690-5-crystal.guo@mediatek.com/ changes since v12: - Change reg_data[3][] to reg_data[SVSB_PHASE_NUM][] - Change MT8192 SVS GPU opp count from 16 to 14 for project requirment - Remove redundant "pd_req = false" in svs_mt8192_banks - Assign svsp->bank_num by ARRAY_SIZE(svs_mt81xx_banks) - Replace `,` with `;` in svs_get_svs_mt8192_platform_data() Roger Lu (7): [v13,1/7]: dt-bindings: soc: mediatek: add mtk svs dt-bindings [v13,2/7]: arm64: dts: mt8183: add svs device information [v13,3/7]: soc: mediatek: SVS: introduce MTK SVS engine [v13,4/7]: soc: mediatek: SVS: add debug commands [v13,5/7]: dt-bindings: soc: mediatek: add mt8192 svs dt-bindings [v13,6/7]: arm64: dts: mt8192: add svs device information [v13,7/7]: soc: mediatek: SVS: add mt8192 SVS GPU driver .../bindings/soc/mediatek/mtk-svs.yaml | 89 + arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 + drivers/soc/mediatek/Kconfig | 10 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-svs.c | 2494 +++++++++++++++++ 6 files changed, 2646 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml create mode 100644 drivers/soc/mediatek/mtk-svs.c