From patchwork Fri Apr 11 05:33:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 28248 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ig0-f199.google.com (mail-ig0-f199.google.com [209.85.213.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 8D3E4212DC for ; Fri, 11 Apr 2014 05:34:35 +0000 (UTC) Received: by mail-ig0-f199.google.com with SMTP id c1sf1505155igq.6 for ; Thu, 10 Apr 2014 22:34:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:message-id:date:from:user-agent :mime-version:to:cc:subject:references:in-reply-to:sender:precedence :list-id:x-original-sender:x-original-authentication-results :mailing-list:list-post:list-help:list-archive:list-unsubscribe :content-type:content-transfer-encoding; bh=4FBrdEfN7GDN2+GAM+wV2UECT6ph7NSE4mUh6C0F/lw=; b=Dpe7Ps5hw539h+w8J9nRQwYT0wZGuYazcCsRPTgzeU+cUqK/Dcrvp58HvpsFuAbj/k vgvcX1zteamsSw45nzg54nanOl3gptIPrkfeLrI4yZGWD3/kw0b9LnklDLOXUttqXXwi er3AkTdDCpmbmzX/F5hzdcpOv7nKsct0dj2AoKvF7K1G4IgbihWnLXOPGK7VLa4TNTmf D8pGZ4H5Bj95+6tb1/AapHS1ctefeNouv0dcTphy2VJE+L5YxlrIZ50fr0cYDhYt/mvm Czrig6C1fw1Mp6r3JpaDPblgHYKyVayRWZomYuii6OcRFksiLgDJs6rCJoo6qQ74PGMZ d0Fg== X-Gm-Message-State: ALoCoQkS4mQoq+cb78fzJn3Yv5jKbap2NQWU/VOd3eM35C5buw9IvnkokDiGfXrPlxr+9OkPiqRV X-Received: by 10.43.141.196 with SMTP id jf4mr9635861icc.9.1397194474711; Thu, 10 Apr 2014 22:34:34 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.98.229 with SMTP id o92ls1482577qge.95.gmail; Thu, 10 Apr 2014 22:34:34 -0700 (PDT) X-Received: by 10.220.133.80 with SMTP id e16mr18155208vct.13.1397194474614; Thu, 10 Apr 2014 22:34:34 -0700 (PDT) Received: from mail-vc0-f178.google.com (mail-vc0-f178.google.com [209.85.220.178]) by mx.google.com with ESMTPS id f17si1103475vco.135.2014.04.10.22.34.34 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 10 Apr 2014 22:34:34 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.178; Received: by mail-vc0-f178.google.com with SMTP id im17so4256886vcb.23 for ; Thu, 10 Apr 2014 22:34:34 -0700 (PDT) X-Received: by 10.52.175.166 with SMTP id cb6mr15012005vdc.1.1397194474481; Thu, 10 Apr 2014 22:34:34 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp26302vcb; Thu, 10 Apr 2014 22:34:34 -0700 (PDT) X-Received: by 10.68.201.67 with SMTP id jy3mr24843497pbc.20.1397194473362; Thu, 10 Apr 2014 22:34:33 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g7si3455003pad.117.2014.04.10.22.34.32; Thu, 10 Apr 2014 22:34:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754227AbaDKFeb (ORCPT + 5 others); Fri, 11 Apr 2014 01:34:31 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:38940 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751084AbaDKFea (ORCPT ); Fri, 11 Apr 2014 01:34:30 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3B5Y0Ed010626; Fri, 11 Apr 2014 00:34:00 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3B5Y0XW005205; Fri, 11 Apr 2014 00:34:00 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Fri, 11 Apr 2014 00:34:00 -0500 Received: from [172.24.190.153] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3B5Xwrl027055; Fri, 11 Apr 2014 00:33:58 -0500 Message-ID: <53477EC5.5080400@ti.com> Date: Fri, 11 Apr 2014 11:03:57 +0530 From: Sekhar Nori User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Russell King - ARM Linux CC: Tony Lindgren , Linux OMAP Mailing List , Linux ARM Mailing List Subject: Re: [PATCH v2 3/3] ARM: OMAP2+: AM43x: L2 cache support References: <20140404101808.GG27282@n2100.arm.linux.org.uk> <53440D73.6060504@ti.com> <20140409162327.GH27282@n2100.arm.linux.org.uk> <534686DF.7070207@ti.com> <20140410120348.GK27282@n2100.arm.linux.org.uk> <53468B8E.9040604@ti.com> <53469C29.8050906@ti.com> <20140410134028.GL27282@n2100.arm.linux.org.uk> In-Reply-To: <20140410134028.GL27282@n2100.arm.linux.org.uk> Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nsekhar@ti.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On Thursday 10 April 2014 07:10 PM, Russell King - ARM Linux wrote: > On Thu, Apr 10, 2014 at 06:57:05PM +0530, Sekhar Nori wrote: >> On Thursday 10 April 2014 05:46 PM, Sekhar Nori wrote: >>> This will work. NS_LOCKDOWN is required for L2C-220 as well and so I was >>> thinking about adding a new l2c220_enable() which will set the >>> NS_LOCKDOWN and then call l2c_enable() >> >> Here is a patch for what I was saying above. >> >> diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h >> index c47ac8f..dc9e03b 100644 >> --- a/arch/arm/include/asm/hardware/cache-l2x0.h >> +++ b/arch/arm/include/asm/hardware/cache-l2x0.h >> @@ -105,6 +105,8 @@ >> #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9) >> #define L2X0_AUX_CTRL_ASSOC_SHIFT 13 >> #define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13) >> +/* L2C-220/310 common bits */ >> +#define L2C_AUX_CTRL_NS_LOCKDOWN BIT(26) >> /* L2C-210 specific bits */ >> #define L210_AUX_CTRL_WRAP_DISABLE BIT(12) >> #define L210_AUX_CTRL_WA_OVERRIDE BIT(23) >> @@ -113,7 +115,6 @@ >> #define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) >> #define L220_AUX_CTRL_FWA_SHIFT 23 >> #define L220_AUX_CTRL_FWA_MASK (3 << 23) >> -#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26) >> #define L220_AUX_CTRL_NS_INT_CTRL BIT(27) >> /* L2C-310 specific bits */ >> #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */ >> @@ -122,7 +123,6 @@ >> #define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) >> #define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16) >> #define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */ >> -#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26) > > NAK. The reason for this split is because the NS lockdown bit is *not* > on L2C-210, and so it does not deserve to be a "common" bit - because it > isn't common to all variants. Okay. > >> @@ -764,7 +776,7 @@ static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) >> power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); >> } >> >> - l2c_enable(base, aux, num_lock); >> + l2c220_enable(base, aux, num_lock); > > My first reaction to this is to say NAK again - I don't want to create > a multi-layered maze of X calls Y calls Z. Who's to say that The 220 > won't need to do something different from 310 in the future? Here is a revised patch which is just an extension of your patch with L2C-220 case handled. I dont really have L2C-220 hardware so even if you want to handle that at a later time, it would be perfectly okay with me. Thanks, Sekhar --- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 6b2a056..34cafe0 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -216,8 +216,6 @@ int __init omap4_l2_cache_init(void) { /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ u32 aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR | - L310_AUX_CTRL_NS_LOCKDOWN | - L310_AUX_CTRL_NS_INT_CTRL | L2C_AUX_CTRL_SHARED_OVERRIDE | L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH; diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index b1f103d..72f41fa 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -498,11 +498,23 @@ static void l2c220_sync(void) raw_spin_unlock_irqrestore(&l2x0_lock, flags); } +static void __init l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock) +{ + /* + * Always enable non-secure access to the lockdown registers - + * we write to them as part of the L2C enable sequence so they + * need to be accessible. + */ + aux |= L220_AUX_CTRL_NS_LOCKDOWN; + + l2c_enable(base, aux, num_lock); +} + static const struct l2c_init_data l2c220_data = { .type = "L2C-220", .way_size_0 = SZ_8K, .num_lock = 1, - .enable = l2c_enable, + .enable = l2c220_enable, .outer_cache = { .inv_range = l2c220_inv_range, .clean_range = l2c220_clean_range, @@ -764,6 +776,13 @@ static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); } + /* + * Always enable non-secure access to the lockdown registers - + * we write to them as part of the L2C enable sequence so they + * need to be accessible. + */ + aux |= L310_AUX_CTRL_NS_LOCKDOWN; + l2c_enable(base, aux, num_lock); if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) { @@ -1027,7 +1046,7 @@ static const struct l2c_init_data of_l2c220_data __initconst = { .way_size_0 = SZ_8K, .num_lock = 1, .of_parse = l2x0_of_parse, - .enable = l2c_enable, + .enable = l2c220_enable, .outer_cache = { .inv_range = l2c220_inv_range, .clean_range = l2c220_clean_range,