From patchwork Wed Mar 27 07:38:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 783489 Received: from mail5.25mail.st (mail5.25mail.st [74.50.62.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45B5225779; Wed, 27 Mar 2024 07:39:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.50.62.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711525179; cv=none; b=lrsEvo9cD0x+64d7YGVdlZ5UHESOnhE0th2uSBQ1oq/FVyChqd+Mg72hWveWTF4Unklgx4ohK0+bHUXvdoznH/mXGthNES3I8uDTaZDbXvjtThtt2YGChbnVG8lPCr4efnk/qTxEuYTBH+9avDZEa5oUmaCuCif3jxmCG0UGgoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711525179; c=relaxed/simple; bh=ImWBqJ7fNxsYzNWMC4Sbo9WClKzU09Z6d4NV3S9LuQM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ua5hIus1p1pF3YeK49gMzZIA2W5v9JAX3I6keBTjIjOz/m84E9pBfxX6CsorVb/QmFJSdgRF73Onwq9Xa18QVxHcuPZjAFNpg6mBOYK2oeRF4uIqC29CMCiZY49L/pJfjxLqkmqfzc4T00Nf0Q+7HXhOe0ysO33qL1FE1/YuLLs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=atomide.com; spf=fail smtp.mailfrom=atomide.com; dkim=pass (2048-bit key) header.d=atomide.com header.i=@atomide.com header.b=XVKUgSWM; arc=none smtp.client-ip=74.50.62.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=atomide.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=atomide.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=atomide.com header.i=@atomide.com header.b="XVKUgSWM" Received: from localhost (91-158-86-216.elisa-laajakaista.fi [91.158.86.216]) by mail5.25mail.st (Postfix) with ESMTPSA id DD9E360434; Wed, 27 Mar 2024 07:39:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=atomide.com; s=25mailst; t=1711525176; bh=ImWBqJ7fNxsYzNWMC4Sbo9WClKzU09Z6d4NV3S9LuQM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XVKUgSWMgermilocoEnT8I5luc6cLQVYNKDUUiUSAOx3u+bgRDNm0DhzLb/IncDA8 wcAg5kWJPWHlxDj4gU95o1QN4yZtrfpuyHRNDQe4bDJEGOJC2eBYofD7cSr4+mNf1a cnptdmpcViKBTZsANGTvfFniPYeXk1+K9RlIieMhZ8+/dH+7xN5nZauFGGP/BEf92b MYRt3xnCKFo/pmeSSzUULbo8TdLg63IXkJLhp+e4OVvhe/Z86sTwPs3i8k24noB0BK 6OngF2LCk2LljKS8GjlaYTQDxbjz/mguAGCUlsCkgjYCkTIYedWFYMwnRabIVjFHPF iAh4j5J609p9w== From: Tony Lindgren To: linux-omap@vger.kernel.org Cc: =?utf-8?q?Beno=C3=AEt_Cousson?= , devicetree@vger.kernel.org Subject: [PATCH 03/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA Date: Wed, 27 Mar 2024 09:38:47 +0200 Message-ID: <20240327073856.21517-4-tony@atomide.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240327073856.21517-1-tony@atomide.com> References: <20240327073856.21517-1-tony@atomide.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -426,13 +426,21 @@ iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { clock-div = <1>; }; - dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_iva_byp_mux"; - clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; + /* CM_CLKSEL_DPLL_IVA */ + clock@1ac { + compatible = "ti,clksel"; + reg = <0x1ac>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_iva_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; + clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; + #clock-cells = <0>; + }; }; dpll_iva_ck: clock@1a0 {