From patchwork Tue Oct 3 10:55:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: MD Danish Anwar X-Patchwork-Id: 729906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C16B4E7544A for ; Tue, 3 Oct 2023 10:56:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239713AbjJCK4r (ORCPT ); Tue, 3 Oct 2023 06:56:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239867AbjJCK4p (ORCPT ); Tue, 3 Oct 2023 06:56:45 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33858EA; Tue, 3 Oct 2023 03:56:40 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 393AuF0X088168; Tue, 3 Oct 2023 05:56:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1696330575; bh=J+Q0ZtjZFk83NaGx62OOqN/1axfwRqE1uczTFxxZV3A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pn3ZxkgqVRt8kjoIQnvSUQNrgl8dHwi45CvkUdg0c7zcojZsIDA0zQBM3oo1uPbEP E71N//Icf/gjTDGVMzsNwze92QvM8+EtcxjadDUcuW805CbO3IkjMFr9fGNnsW1KuX Eq89FCcPGkQN3BGomxB9nGQD2pT/OX3n6m/qXbmk= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 393AuFvH093753 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 3 Oct 2023 05:56:15 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 3 Oct 2023 05:56:15 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 3 Oct 2023 05:56:15 -0500 Received: from fllv0122.itg.ti.com (fllv0122.itg.ti.com [10.247.120.72]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 393AuEdJ123329; Tue, 3 Oct 2023 05:56:14 -0500 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.199]) by fllv0122.itg.ti.com (8.14.7/8.14.7) with ESMTP id 393AuEbo007928; Tue, 3 Oct 2023 05:56:14 -0500 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Peng Fan , Udit Kumar , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Neil Armstrong , Arnd Bergmann , Konrad Dybcio , Geert Uytterhoeven , Bjorn Andersson , Will Deacon , Catalin Marinas , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Andrew Lunn , , , , Tero Kristo , , , , MD Danish Anwar Subject: [PATCH v4 4/4] arm64: defconfig: Enable TI_ICSSG_PRUETH Date: Tue, 3 Oct 2023 16:25:39 +0530 Message-ID: <20231003105539.1698436-5-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231003105539.1698436-1-danishanwar@ti.com> References: <20231003105539.1698436-1-danishanwar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The Programmable Real-time Unit and Industrial Communication Subsystem Gigabit (PRU_ICSSG) is a low-latency microcontroller subsystem in the TI K3 SoCs such as AM654x, AM64x. This subsystem is provided for the use cases like implementation of custom peripheral interfaces, offloading of tasks from the other processor cores of the SoC, etc. Currently AM654x-EVM uses ICSSG driver. Signed-off-by: MD Danish Anwar --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 66bfbef73324..b7cbc7b38d63 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -368,6 +368,7 @@ CONFIG_SNI_NETSEC=y CONFIG_STMMAC_ETH=m CONFIG_DWMAC_TEGRA=m CONFIG_TI_K3_AM65_CPSW_NUSS=y +CONFIG_TI_ICSSG_PRUETH=m CONFIG_QCOM_IPA=m CONFIG_MESON_GXL_PHY=m CONFIG_AQUANTIA_PHY=y