From patchwork Fri Feb 4 07:33:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 540004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 000D1C433FE for ; Fri, 4 Feb 2022 07:33:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352264AbiBDHdo (ORCPT ); Fri, 4 Feb 2022 02:33:44 -0500 Received: from muru.com ([72.249.23.125]:46376 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352180AbiBDHdn (ORCPT ); Fri, 4 Feb 2022 02:33:43 -0500 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 4BCEF8171; Fri, 4 Feb 2022 07:33:26 +0000 (UTC) From: Tony Lindgren To: linux-omap@vger.kernel.org Cc: =?utf-8?q?Beno=C3=AEt_Cousson?= , devicetree@vger.kernel.org, Stephen Boyd , Tero Kristo Subject: [PATCH 1/4] ARM: dts: Add clksel node for am3 ehrpwm Date: Fri, 4 Feb 2022 09:33:30 +0200 Message-Id: <20220204073333.18175-2-tony@atomide.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220204073333.18175-1-tony@atomide.com> References: <20220204073333.18175-1-tony@atomide.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Let's add a clksel node for the component clocks to avoid devicetree unique_unit_address warnings. The component clocks can now get IO address from the parent clksel node. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-clocks.dtsi | 47 ++++++++++++++++------------ 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -93,28 +93,35 @@ rng_fck: rng_fck { clock-div = <1>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; + clock@664 { + compatible = "ti,clksel"; + reg = <0x664>; + #clock-cells = <2>; + #address-cells = <0>; + + ehrpwm0_tbclk: clock-ehrpwm0-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <0>; + }; - ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; + ehrpwm1_tbclk: clock-ehrpwm1-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <1>; + }; - ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; + ehrpwm2_tbclk: clock-ehrpwm2-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <2>; + }; }; }; &prcm_clocks {