From patchwork Tue Jul 20 14:41:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 483624 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2890AC6377B for ; Tue, 20 Jul 2021 15:12:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E992611F2 for ; Tue, 20 Jul 2021 15:12:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234411AbhGTOcG (ORCPT ); Tue, 20 Jul 2021 10:32:06 -0400 Received: from mail-io1-f42.google.com ([209.85.166.42]:43711 "EHLO mail-io1-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240090AbhGTOBD (ORCPT ); Tue, 20 Jul 2021 10:01:03 -0400 Received: by mail-io1-f42.google.com with SMTP id k16so24188632ios.10; Tue, 20 Jul 2021 07:41:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XBmEtxGuro5AHDRV4MlIOBSIJE60xpP6Q488vaMtT4w=; b=SYHWdQMfROgL2XdFLoubttcvqJqQqijLuVEaeXh8WtEZCr5jBxI3vpOkNLgauSMtC8 yl8HMsv2zoEm8DDR4aMd+xYclgJGTiSQAsvCutpfgrmASX4bJVUrfI/ZsGT3nYn/h/XF Swl5INsOOBpB3JBovVmmhu85Q2mamzJT8/0MGnHWXYzu9gpU1MrkQJSNSGXMJcMpvUTv YlMbIAhbRVSfID7LY7Ay/jl4gWhe7270TNcpjFN8tWeaXfhH+kwguPGjOZ6zVZil82b+ NSZ/8pE4K67Dku7i0Ib7XN2EpgfV6W6i8qbE5JSW129Xy+xASwGcDsZS0JFY54jdPkuf f4jA== X-Gm-Message-State: AOAM531z+WIVjZiVmfsBOVpZXvxk4lIbvUxi+9z7yVB2xDNkYE5/a3Uy O/JgYMIbAAfA2mnQjoEBGg== X-Google-Smtp-Source: ABdhPJxooJfH/EtsqVVp9aWaE7jnvJiJKvu2tMzpZa406I+JYIozF7V3Rmk+KzkVPfszh9YcgMuFVA== X-Received: by 2002:a6b:e60f:: with SMTP id g15mr22562813ioh.48.1626792086375; Tue, 20 Jul 2021 07:41:26 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.248]) by smtp.googlemail.com with ESMTPSA id 10sm2091407iln.39.2021.07.20.07.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 07:41:25 -0700 (PDT) From: Rob Herring To: Viresh Kumar , Tony Lindgren Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Be?= =?utf-8?q?no=C3=AEt_Cousson?= , linux-omap@vger.kernel.org, Georgi Djakov , Shawn Guo , Sascha Hauer , Leonard Crestez , dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Subject: [PATCH v3 2/3] dt-bindings: Clean-up OPP binding node names in examples Date: Tue, 20 Jul 2021 08:41:20 -0600 Message-Id: <20210720144121.66713-2-robh@kernel.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210720144121.66713-1-robh@kernel.org> References: <20210720144121.66713-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org In preparation to convert OPP bindings to DT schema, clean-up a few OPP binding node names in the binding examples. Cc: Georgi Djakov Cc: Shawn Guo Cc: Sascha Hauer Cc: Leonard Crestez Cc: dri-devel@lists.freedesktop.org Cc: linux-pm@vger.kernel.org Acked-by: Viresh Kumar Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 2 +- Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml | 2 +- .../devicetree/bindings/interconnect/fsl,imx8m-noc.yaml | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 0f73f436bea7..4bea51d1e7ea 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -136,7 +136,7 @@ examples: resets = <&reset 0>, <&reset 1>; }; - gpu_opp_table: opp_table0 { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-533000000 { diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 696c17aedbbe..d209f272625d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -160,7 +160,7 @@ examples: #cooling-cells = <2>; }; - gpu_opp_table: opp_table0 { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-533000000 { diff --git a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml index a8873739d61a..b8204ed22dd5 100644 --- a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml +++ b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml @@ -81,10 +81,10 @@ examples: noc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-133M { + opp-133333333 { opp-hz = /bits/ 64 <133333333>; }; - opp-800M { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; };