From patchwork Mon Jul 13 11:01:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235387 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2727060ilg; Mon, 13 Jul 2020 04:03:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycCFVmKPRAbWVrWauUQHJIyxohlW1R7CMaDz7032KODoJYItJfR9BUrqVGkMbO/GzcnM+7 X-Received: by 2002:a17:906:456:: with SMTP id e22mr66708978eja.178.1594638185249; Mon, 13 Jul 2020 04:03:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638185; cv=none; d=google.com; s=arc-20160816; b=LV1GuQj1iNg0XZ5XHQ3CYBGICGuQyHDaY0LKw2qzchSE74TZs29Oa7hZvp13/hDzCX Vv3+eNTksMzuLHjvA0uazxu+di0zTmytp6NKc/hbSQFl6kMrFf2bzG9ckv4CSSKwgz4J 4UUXThuTBLrSAVGVfSG4lTmu3TmgNsIQknoOgJBfpFaAckF6CTvfiqPvDE9wf/4lOoL3 Yy2fXNupfwLsOisFI4zEsOBgeW8GRaF/iRN5FmvpinumRNWMb3ro7lxV3YyM4/vXRhzC xgkwieaDUvcI0hXZm7RsjbWP8QZg+ff+McHRMwoxPbVr7xaVnXDwQ/YdnzBXrwcEIfrt 9YAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=o7DMocX7rlMLQL03fwQQZCPBjquUDY+oSrh6N/Sv4XY=; b=WrdEodVyI8NLCAZshtgHa8Fi2346OvNn6Rz7PZQknunG3r6J/4dNNC+jZOHZaeXBXg IkBcUrrrzJCZ7Yd1l6m2qGCo/SrFbLsG1e/bEGkKGMk5yf/XknOJM0oK2N3V8tOMjT+S sIbiv/5h9Fz2VmBS0r6ckzpu6OKiPpBccPqwE6KaIae9n6kH3tuvJ9m9VvNHNo2CBQwC LEPS1ub5BY+7Q/2vBeM95Vp/17K61x+lBLuEmbvsQCKAYXsjHY0y9x8Y4Pj7Z/ZAxV2R YGK5HpePZK3ig4WH7IR8stEwbjxGaoIhwoeM66CYtRTXVgJylMoi0/mDSIWOA2AmGr+M xkjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DA6YaZqJ; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b8si11797917edz.89.2020.07.13.04.03.05; Mon, 13 Jul 2020 04:03:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DA6YaZqJ; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729732AbgGMLCf (ORCPT + 4 others); Mon, 13 Jul 2020 07:02:35 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:47008 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729727AbgGMLCe (ORCPT ); Mon, 13 Jul 2020 07:02:34 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB2OnT071601; Mon, 13 Jul 2020 06:02:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638144; bh=o7DMocX7rlMLQL03fwQQZCPBjquUDY+oSrh6N/Sv4XY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DA6YaZqJexQU1tj4/4laZBdRUtY/HyKqXkNcvk6Jzs4Xsw4O0P0f3TzepQavJy8iG Xy04hMdUBNADbOctVnklh+B5PfI4IJXzONhKJKi6/ec+xgot+3se6ajsMKjUKX7Qkr neGabss7uNEdi7ToEOiMLSPCo50cjL5rw6WIFsEk= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB2OpY005673; Mon, 13 Jul 2020 06:02:24 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:02:23 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:02:23 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVk031460; Mon, 13 Jul 2020 06:02:20 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Date: Mon, 13 Jul 2020 16:31:37 +0530 Message-ID: <20200713110141.13156-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713110141.13156-1-kishon@ti.com> References: <20200713110141.13156-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add host mode dt-bindings for TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml new file mode 100644 index 000000000000..d7b60487c6c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI Host (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I + +allOf: + - $ref: "cdns-pcie-host.yaml#" + +properties: + compatible: + enum: + - ti,j721e-pcie-host + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: cfg + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + vendor-id: + const: 0x104c + + device-id: + const: 0xb00d + + msi-map: true + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - vendor-id + - device-id + - msi-map + - dma-coherent + - dma-ranges + - ranges + - reset-gpios + - phys + - phy-names + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + };