From patchwork Mon Jan 14 13:24:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155471 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3656594jaa; Mon, 14 Jan 2019 05:26:44 -0800 (PST) X-Google-Smtp-Source: ALg8bN7EjDqNi/PL8J46ugyiLBgU69sXZndOG3XazO+oR0FmwTT17Gxq/2hlwPmfeGzWjebblWEe X-Received: by 2002:a17:902:33c1:: with SMTP id b59mr25106387plc.220.1547472404811; Mon, 14 Jan 2019 05:26:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472404; cv=none; d=google.com; s=arc-20160816; b=vGbJUGdEhrlxpCGDRHVtWZZMnG+PBxA2fTvZTCxPxYyu1Z3UgY8gXLUi0PI5Ie36l/ 3BJ2OWsvXPmSMdHkvpH/7HGivCiyPeSPOLD/I8dKb5eMTlchMcKhd8FEsnOT+TvIRxvG rTP5OW/2YBlnGX4agEytK2Jt6By4ex9taNByT9Scv04M5EftDHU42cW5wUrFP+QXvbtC grPtNjFt8wybIXXbwW/ArEbfohzux57brYpxTXmZRWzQVnUNkc9PNRFXkCZjy3xxOP4U Cic7H2yEkmf9k4no6th37Rn4gpiLkH8N4PcpgYvVHN9tv6VVr+gbGZQMwjjWSseTriHc YSTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=D3SpjZ5R1aRjfVZ7VM2I5QEfz4WOvJBUIsbp05h8aqY=; b=B8PVOjC1QlZdpCAzVrFUZNnx2/e9wSKqAV2P/uCUJ2tV8+MgDgt/XhNZ1jKtGfgky8 lhospmCTw7c99tgFVUC89Us54RBqC9GpW+BbEHIhwM8nuMIKoazL807F+GWZLM6lQTZp 8Ffo37jvt3CloMeKk4C+ISMclP2Er55nOTTpeuNLmCv2pNSYVlBkwfSQ54GmhcJ2SIkc DNbIVdsvvzTzhJbwFZoIW2ezoABEM+M/lngkq3xG1aWOnJJq3CIPqzgGOHIX3L95eVrM VJborvuFjpmFhl5ZdO/tkDwDcpI21k1osUWYk12cU6zTZmwdXCsbxNdskdA0WnBeStP3 MsaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ogUqVufQ; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o13si319419pgp.540.2019.01.14.05.26.44; Mon, 14 Jan 2019 05:26:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ogUqVufQ; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726850AbfANN0m (ORCPT + 5 others); Mon, 14 Jan 2019 08:26:42 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37436 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726839AbfANN0l (ORCPT ); Mon, 14 Jan 2019 08:26:41 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDPimd098134; Mon, 14 Jan 2019 07:25:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472345; bh=D3SpjZ5R1aRjfVZ7VM2I5QEfz4WOvJBUIsbp05h8aqY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ogUqVufQPF4gH6zHydPgoxdYDw/n+mQCs5EYKOMAVsJV0lAmfpZtpIUkjhHPmFqcN Dsli75pOExCF7Gc5hFeGXpulA4twdXnrTKmiXS2C37scp/zqNcgn2+z50ptGDA/rhc c2ZW7+Rtpdr22l/bkYPZqGa/1pi6B3vRQeIj9iMo= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDPi0Y056711 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:44 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:44 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:44 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWW028516; Mon, 14 Jan 2019 07:25:40 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 10/24] PCI: dwc: Enable iATU unroll for endpoint too Date: Mon, 14 Jan 2019 18:54:10 +0530 Message-ID: <20190114132424.6445-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org iatu_unroll_enabled flag is set only for Designware in host mode. However iATU unroll can be applicable for endpoint mode too. Set iatu_unroll_enabled flag in dw_pcie_setup which is common for both host mode and endpoint mode. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-ep.c | 4 ---- .../pci/controller/dwc/pcie-designware-host.c | 19 ------------------- drivers/pci/controller/dwc/pcie-designware.c | 19 +++++++++++++++++++ 3 files changed, 19 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 7a2925a16ab8..d5144781005b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -515,10 +515,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); return -EINVAL; } - if (pci->iatu_unroll_enabled && !pci->atu_base) { - dev_err(dev, "atu_base is not populated\n"); - return -EINVAL; - } ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); if (ret < 0) { diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d7184e1a7d92..1fb7eece78ab 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -629,17 +629,6 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) -{ - u32 val; - - val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); - if (val == 0xffffffff) - return 1; - - return 0; -} - void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val, ctrl, num_ctrls; @@ -693,14 +682,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * we should not program the ATU here. */ if (!pp->ops->rd_other_conf) { - /* Get iATU unroll support */ - pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); - dev_dbg(pci->dev, "iATU unroll: %s\n", - pci->iatu_unroll_enabled ? "enabled" : "disabled"); - - if (pci->iatu_unroll_enabled && !pci->atu_base) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 93ef8c31fb39..78539452c265 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -339,6 +339,17 @@ int dw_pcie_link_up(struct dw_pcie *pci) (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); } +static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); + if (val == 0xffffffff) + return 1; + + return 0; +} + void dw_pcie_setup(struct dw_pcie *pci) { int ret; @@ -347,6 +358,14 @@ void dw_pcie_setup(struct dw_pcie *pci) struct device *dev = pci->dev; struct device_node *np = dev->of_node; + /* Get iATU unroll support */ + pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); + dev_dbg(pci->dev, "iATU unroll: %s\n", + pci->iatu_unroll_enabled ? "enabled" : "disabled"); + + if (pci->iatu_unroll_enabled && !pci->atu_base) + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) lanes = 0;