From patchwork Mon Jan 7 06:41:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154855 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3171057ljp; Sun, 6 Jan 2019 22:43:33 -0800 (PST) X-Google-Smtp-Source: AFSGD/UOzzaB5kGdbduWit56fbVfVg82qU0HQsM7DX376NskQ42vmjCk7i7xvDjRqt59XVYXNvBr X-Received: by 2002:a62:2cf:: with SMTP id 198mr62317168pfc.67.1546843413128; Sun, 06 Jan 2019 22:43:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546843413; cv=none; d=google.com; s=arc-20160816; b=yzVHojIUGsJcNcbQfkq/XkG/CvzhhILpupOe2xS1Jnc9s2Q1OAr0hyO0fl52cz/nQB 1qzkBAh1UjjMM49rf9C8poWjQo27Qyo803vYr363v5KUiEz9DcyrQuRjNTK/3sh7L/sw MggZCl5jT3zYJrAyhnYmsTHhoDfg4qULlBO4aG94LUOu1aaeWd8jplEGzcp9jz9WNOLl 6bs6lPRDzm7x4AVEIJ9RzEOxLZxtW3ZOYSdSkoaajI6o1NaycwGgOx8CF/aTA/a8vJzP K5pGAIGEOg7rZx0+lqwZXVbrdxwhFOr1YtxVs8gCFNRSz1OQ4FfUOaFqe4GCbpKExnG4 amlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=UxFV2AA/OxJ+RGbF6mGrC+ScIM/GAuGJn+bhMgD6qEM=; b=P64qKUVRHvTFu0AP2GyXDx7u1rNrbRat+g3kc4QAJp+eMmJJN4ymwiYAGzbp1sEKtY NSOEe9cULqT7mgpxUqMCtEZODMqZuMv8Wpqu7NcfYPNUhwoonbhdJmmQ8RH7rCV1TmkL BOu1bhwbVbYMn1b9dJhyw0/c14toDjev7944ltc6CLhWzp433r+w1GesjRxrGG+Q5i4r AiPsVV37NCzRc+AOdCb6nC/MdQ8CrP4E+xurISA62orVhteLjDuRifR6RNdnPRfvnJl+ Tv4qvUGvqjkvWOntTCWOZ+j+1svTikA5R/PqzTBYD1Ij0wjNdmM3IjDGwPYa5BCySOhZ I+7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=t5cLz4cA; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f75si7494493pff.131.2019.01.06.22.43.32; Sun, 06 Jan 2019 22:43:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=t5cLz4cA; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725771AbfAGGn3 (ORCPT + 5 others); Mon, 7 Jan 2019 01:43:29 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:40958 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726537AbfAGGn1 (ORCPT ); Mon, 7 Jan 2019 01:43:27 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x076h1se058868; Mon, 7 Jan 2019 00:43:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1546843381; bh=UxFV2AA/OxJ+RGbF6mGrC+ScIM/GAuGJn+bhMgD6qEM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=t5cLz4cAmg4s3+2A/8tCs9Ll7f8dHxNtToHd4BozQ3Ycafmms1BT7lH5Mq8Ozt0tp fYG+0z+ehXDym+7TXJroLrsDSLQXBzJuece+auPpHxQ8lAyC8G76DEcwKZqHfDK5lH HzJ0LNw3sQM12JxEekDp4QhRGHZjNg4rF8CHzo24= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x076h04N048436 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 7 Jan 2019 00:43:00 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 7 Jan 2019 00:43:00 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 7 Jan 2019 00:43:00 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x076gfo0002672; Mon, 7 Jan 2019 00:42:56 -0600 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Bjorn Helgaas , Gustavo Pimentel , Alan Douglas , Shawn Lin CC: Jingoo Han , Heiko Stuebner , Cyrille Pitchen , Jia-Ju Bai , , , , , , Subject: [PATCH 03/15] PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops Date: Mon, 7 Jan 2019 12:11:36 +0530 Message-ID: <20190107064148.10152-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190107064148.10152-1-kishon@ti.com> References: <20190107064148.10152-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Populate ->get_features() dw_pcie_ep_ops to return the EPC features supported by Designware PCIe endpoint controller. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-plat.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index c12bf794d69c..bd0516afc86f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -100,9 +100,22 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +static const struct pci_epc_features dw_plat_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = true, +}; + +static const struct pci_epc_features* +dw_plat_pcie_get_features(struct dw_pcie_ep *ep) +{ + return &dw_plat_pcie_epc_features; +} + static struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dw_plat_pcie_ep_init, .raise_irq = dw_plat_pcie_ep_raise_irq, + .get_features = dw_plat_pcie_get_features, }; static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,