From patchwork Mon Feb 5 12:50:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 126861 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1944891ljc; Mon, 5 Feb 2018 04:55:30 -0800 (PST) X-Google-Smtp-Source: AH8x227V4eUSNq3gyUr6t+NpucLm2A2jdvOqJlQFd5qv8++iAqszgGxqOWKdqSeMNtDhuCZNGykg X-Received: by 10.98.253.5 with SMTP id p5mr49030931pfh.132.1517835330806; Mon, 05 Feb 2018 04:55:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517835330; cv=none; d=google.com; s=arc-20160816; b=WgD9sLLNznrqP4m6R3AZEMmtJ6afZF19ZV6sE3GBk0j51n5XFOyXe/vXu0ELX34aN2 JdplfcyAtErQdaz+iN38u2zxqbv4mdjfD6UTKjCmArgctQ34il1emo1PUX3xbgpN+yOU rJGbA2t9fCiuae+yOLgUeXP/9GdAP4ZbJm2PkEVjyQ0I2OMghv3usy3FNEbZR8Ar0mWk 0/GJrLD0vJkQQ+6/Ss9a56UV4Zb9wgxW7Xss5o6WQ2A89kPutyhJA+zpQJPybJ4K8qaV JCkhBWNyAZM7B0vp/Ym5vBJ/HimL3Aj3lzBc4no/ciOgBWaEWAC9SgF2Vyz2rkC8imCY 5Cuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=26HG49b1LyADgqL68I07aMavhl5PNMV5EHW98+f+6SI=; b=vdFn9N1et2KLTGrJ0N8PI/RBwSGRWuNQfRqlZAQD0F27EiAckE7izygQgxc38wMnp9 SgX62M9IZVqfC3ukb3fSPUoQfn5Ok2uIvCJ4Wa096jI8TvOARQ3LR6cRUxifPjmigsSM yWA7GgbJSmd4wiOt29j/lQ/3NPD26KrcBOJRHZxOGDKk2iXpnt76NgdKVjSlpSldLk4S X7b9nw8etZMukRDjbQOpXsnKXQZHmkV3iErOcAZXrOdmUTeqtQ5O6Tb4/PrTG1FCN04f lNy+Z0/Cja9PsyARPBWNS91C7qqccbECGqzMuzFPRW29obvrHzLGDaAbb6lyck5/t6RH rHHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=gy5oTA4N; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a80si6833656pfa.6.2018.02.05.04.55.30; Mon, 05 Feb 2018 04:55:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=gy5oTA4N; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753015AbeBEMz2 (ORCPT + 5 others); Mon, 5 Feb 2018 07:55:28 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:63854 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752866AbeBEMv0 (ORCPT ); Mon, 5 Feb 2018 07:51:26 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w15Cotl8011260; Mon, 5 Feb 2018 06:50:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517835055; bh=5sDFblgRSi57wMKxSqtDf8n0K2GIFFnj9FmoCU0Wpm8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gy5oTA4Nzx7ebfq73EVoKSE8lBqIYyhh9MWTtFyVYwrT+pB+G1mc+aY6LV63UMCpO VWnBG52KlyUlGRsCJRhsXgdEcAKGHf90gmkmBDDcl4p1d/KFoIwyXg9gashL2mOacj 0wdABUtXFFSkokrR+G6mNd8R4b2ARw2OADD99Dg4= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CotDI006733; Mon, 5 Feb 2018 06:50:55 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 5 Feb 2018 06:50:55 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 5 Feb 2018 06:50:54 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CoaGZ023963; Mon, 5 Feb 2018 06:50:51 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Adrian Hunter CC: Rob Herring , Mark Rutland , Russell King , Kishon Vijay Abraham I , , , , , Subject: [PATCH v2 04/16] mmc: sdhci-omap: Add tuning support Date: Mon, 5 Feb 2018 18:20:17 +0530 Message-ID: <20180205125029.21570-5-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205125029.21570-1-kishon@ti.com> References: <20180205125029.21570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org MMC tuning procedure is required to support SD card UHS1-SDR104 mode and EMMC HS200 mode. SDR104/HS200 DLL Tuning Procedure for AM572x platform is mentioned in Figure 25-51. SDR104/HS200 DLL Tuning Procedure of AM572x Sitara Processors Silicon Revision 2.0, 1.1 TRM (SPRUHZ6I - October 2014–Revised April 2017 [1]). The tuning function sdhci_omap_execute_tuning() will only be called by the MMC/SD core if the corresponding speed modes are supported by the OMAP silicon which is set in the mmc host "caps" field. [1] -> http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf Signed-off-by: Kishon Vijay Abraham I Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-omap.c | 130 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index 86b6cc0a5380..36e0626d3de2 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -37,6 +37,13 @@ #define CON_INIT BIT(1) #define CON_OD BIT(0) +#define SDHCI_OMAP_DLL 0x0134 +#define DLL_SWT BIT(20) +#define DLL_FORCE_SR_C_SHIFT 13 +#define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT) +#define DLL_FORCE_VALUE BIT(12) +#define DLL_CALIB BIT(1) + #define SDHCI_OMAP_CMD 0x20c #define SDHCI_OMAP_PSTATE 0x0224 @@ -63,12 +70,16 @@ #define SDHCI_OMAP_AC12 0x23c #define AC12_V1V8_SIGEN BIT(19) +#define AC12_SCLK_SEL BIT(23) #define SDHCI_OMAP_CAPA 0x240 #define CAPA_VS33 BIT(24) #define CAPA_VS30 BIT(25) #define CAPA_VS18 BIT(26) +#define SDHCI_OMAP_CAPA2 0x0244 +#define CAPA2_TSDR50 BIT(13) + #define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */ #define SYSCTL_CLKD_MAX 0x3FF @@ -77,6 +88,8 @@ #define IOV_3V0 3000000 /* 300000 uV */ #define IOV_3V3 3300000 /* 330000 uV */ +#define MAX_PHASE_DELAY 0x7C + struct sdhci_omap_data { u32 offset; }; @@ -198,6 +211,120 @@ static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host, } } +static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host, + int count) +{ + int i; + u32 reg; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); + reg |= DLL_FORCE_VALUE; + reg &= ~DLL_FORCE_SR_C_MASK; + reg |= (count << DLL_FORCE_SR_C_SHIFT); + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); + + reg |= DLL_CALIB; + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); + for (i = 0; i < 1000; i++) { + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); + if (reg & DLL_CALIB) + break; + } + reg &= ~DLL_CALIB; + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); +} + +static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host) +{ + u32 reg; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); + reg &= ~AC12_SCLK_SEL; + sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); + reg &= ~(DLL_FORCE_VALUE | DLL_SWT); + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); +} + +static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + struct device *dev = omap_host->dev; + struct mmc_ios *ios = &mmc->ios; + u32 start_window = 0, max_window = 0; + u8 cur_match, prev_match = 0; + u32 length = 0, max_len = 0; + u32 phase_delay = 0; + int ret = 0; + u32 reg; + + pltfm_host = sdhci_priv(host); + omap_host = sdhci_pltfm_priv(pltfm_host); + dev = omap_host->dev; + + /* clock tuning is not needed for upto 52MHz */ + if (ios->clock <= 52000000) + return 0; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2); + if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50)) + return 0; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); + reg |= DLL_SWT; + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); + + while (phase_delay <= MAX_PHASE_DELAY) { + sdhci_omap_set_dll(omap_host, phase_delay); + + cur_match = !mmc_send_tuning(mmc, opcode, NULL); + if (cur_match) { + if (prev_match) { + length++; + } else { + start_window = phase_delay; + length = 1; + } + } + + if (length > max_len) { + max_window = start_window; + max_len = length; + } + + prev_match = cur_match; + phase_delay += 4; + } + + if (!max_len) { + dev_err(dev, "Unable to find match\n"); + ret = -EIO; + goto tuning_error; + } + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); + if (!(reg & AC12_SCLK_SEL)) { + ret = -EIO; + goto tuning_error; + } + + phase_delay = max_window + 4 * (max_len >> 1); + sdhci_omap_set_dll(omap_host, phase_delay); + + goto ret; + +tuning_error: + dev_err(dev, "Tuning failed\n"); + sdhci_omap_disable_tuning(omap_host); + +ret: + sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + return ret; +} + static int sdhci_omap_card_busy(struct mmc_host *mmc) { u32 reg, ac12; @@ -299,6 +426,8 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc, static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host, u8 power_mode) { + if (omap_host->bus_mode == MMC_POWER_OFF) + sdhci_omap_disable_tuning(omap_host); omap_host->power_mode = power_mode; } @@ -635,6 +764,7 @@ static int sdhci_omap_probe(struct platform_device *pdev) sdhci_omap_start_signal_voltage_switch; host->mmc_host_ops.set_ios = sdhci_omap_set_ios; host->mmc_host_ops.card_busy = sdhci_omap_card_busy; + host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning; sdhci_read_caps(host); host->caps |= SDHCI_CAN_DO_ADMA2;