From patchwork Sat Aug 5 20:52:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 109488 Delivered-To: patch@linaro.org Received: by 10.140.101.6 with SMTP id t6csp991604qge; Sat, 5 Aug 2017 13:53:22 -0700 (PDT) X-Received: by 10.98.43.78 with SMTP id r75mr6770673pfr.269.1501966402049; Sat, 05 Aug 2017 13:53:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501966402; cv=none; d=google.com; s=arc-20160816; b=lopWEVf5+n4db0AwN6K/2g2idRKGcjFi5iL8B68dCRPJ/B2NKHvgSByVZ1M+4izfjR Kl40/AnvsFef3UyhrQv8X0OyH8IlwrQcBjeLNV6a9CFV+aP/vTstgD46W1woKZ1LTu5p OM7AfEsZLxgUr3hZYUs7e44D3OKo6hJKnRl5cxbIPjdbjb6glmDLz6LXxtNShkk8R+Yu grOef3X4SNiBMI/+AWwpPsdKfhesncUYdP8irXyTOhJkZTAw88qKcr821duOY/gPg7d7 EAFWM4JYsLkvQN1KkMOcHATcQLaCr0y6j+zAMwqZTJzc0D+p0xlqF0JsmRaAvy+13FfZ jqLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=VAJEK0I5rbnq0Fr3r38kk7clkQKG53mVhzQl4rqt5dI=; b=JfEDlV/LQtVwm2cnssKkpq6TAspIACwah1g0K0P76vXSPhC0tgTltKF0rBwwWkppJQ Sdbuyu8mTe8xYUxWmAjBUIgAZdNAnCbvDaMLdr7B2mGfTtGKzF0S4Po9DYZ98hZ0Uoqc Lnm3+eDAfKdQQjH2dymJvzjqzEvMBrBrlqPiiInnaw6RjbgbN7R4UgH6ba28ZWplm/6D TCf6dXBIj6FMW7RGDiHy+SNVft9ykvWyoB3SxK8/vCJSqmfU0EYOuWLD2XfKRVSUAI+f FKy0HJvPFZQSoXcfr8dYp0iadjh2QEy9MMhCzPjNyHKcd85BNG0/k9nMxgam0iveMRQG eKVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.b=jtVDzefv; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t11si2480065pgo.694.2017.08.05.13.53.21; Sat, 05 Aug 2017 13:53:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.b=jtVDzefv; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752280AbdHEUxN (ORCPT + 3 others); Sat, 5 Aug 2017 16:53:13 -0400 Received: from mail-wr0-f171.google.com ([209.85.128.171]:33005 "EHLO mail-wr0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751900AbdHEUxL (ORCPT ); Sat, 5 Aug 2017 16:53:11 -0400 Received: by mail-wr0-f171.google.com with SMTP id v105so27162431wrb.0 for ; Sat, 05 Aug 2017 13:53:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z7AJAzwrv8i6psYuqzfsm9AF3MgwmVusZzTSffJgUF0=; b=jtVDzefvCj/FRmySfR+47JZEidHY1m7dWug6s9xbBiQFlqXT7OgEm3S6eeybCsFj4c N+1kiaXvxJ559zxLrOmEpWvLFwjCRfhAZUqJE1YM5WCINrqv2z5erXVzywUauDuqu6Gd MG2QiQ+C9MUHdiCvaJo4nKgI9TBAHwBz4ehgs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z7AJAzwrv8i6psYuqzfsm9AF3MgwmVusZzTSffJgUF0=; b=uCSOFpXw3Nf2v++a5YSZs2m99ztqK9UUFUht3e/plvWdJRG7s7yhREOknNwTafU2O0 p5q8gtHbvoQWRYLv/jTDdQDcnfxdX9MOE9XE7Pn4iov0uvZ0H52UwUvex6KMB3AmwRpQ 7PUmSa0NQDJXyYSz3MCtCm9Y9mAKoAD20VSBtj1YVqSTBT4GDYvT888LYbTG2Z3+ZbtZ oHYq5tinuGJbMTqV4aH5sDGB2d9l0QC3Sxj1QJDfzCQia9NP/fZV8Dfdnc23vh3GxZ6U k6hwJNEWscHMEtKvo+Sqt/XnJi99V4VsBf05NqdARLMmuTzPsBr6u2t6FBw8prjis2O8 pzFw== X-Gm-Message-State: AIVw111MADTsf/fp4PYyppPnhN3cFO09T4i4LnoH2X4AY14BOHPv/VwF zwNY8Tww+P7htgMo X-Received: by 10.223.163.16 with SMTP id c16mr5069436wrb.173.1501966390426; Sat, 05 Aug 2017 13:53:10 -0700 (PDT) Received: from localhost.localdomain ([160.77.147.147]) by smtp.gmail.com with ESMTPSA id v62sm2601775wmd.2.2017.08.05.13.53.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 05 Aug 2017 13:53:09 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux@armlinux.org.uk, linux-omap@vger.kernel.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, krzk@kernel.org, jason@lakedaemon.net, arm@kernel.org, andrew@lunn.ch, gregory.clement@free-electrons.com, sebastian.hesselbarth@gmail.com, tony@atomide.com, baohua@kernel.org, horms@verge.net.au, magnus.damm@gmail.com, vireshk@kernel.org, shiraz.linux.kernel@gmail.com, patrice.chotard@st.com, nico@linaro.org, dave.martin@arm.com, marc.zyngier@arm.com Cc: Ard Biesheuvel Subject: [PATCH 01/15] ARM: assembler: introduce adr_l, ldr_l and str_l macros Date: Sat, 5 Aug 2017 21:52:08 +0100 Message-Id: <20170805205222.19868-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170805205222.19868-1-ard.biesheuvel@linaro.org> References: <20170805205222.19868-1-ard.biesheuvel@linaro.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Like arm64, ARM supports position independent code sequences that produce symbol references with a greater reach than the ordinary adr/ldr instructions. Currently, we use open coded instruction sequences involving literals and arithmetic operations. Instead, we can use movw/movt pairs on v7 CPUs, circumventing the D-cache entirely. For older CPUs, we can emit the literal into a subsection, allowing it to be emitted out of line while retaining the ability to perform arithmetic on label offsets. E.g., on pre-v7 CPUs, we can emit a PC-relative reference as follows: ldr , 222f 111: add , , pc .subsection 1 222: .long - (111b + 8) .previous This is allowed by the assembler because, unlike ordinary sections, subsections are combined into a single section into the object file, and so the label references are not true cross-section references that are visible as relocations. Note that we could even do something like add , pc, #(222f - 111f) & ~0xfff ldr , [, #(222f - 111f) & 0xfff] 111: add , , pc .subsection 1 222: .long - (111b + 8) .previous if it turns out that the 4 KB range of the ldr instruction is insufficient to reach the literal in the subsection, although this is currently not a problem (of the 98 objects built from .S files in a multi_v7_defconfig build, only 11 have .text sections that are over 1 KB, and the largest one [entry-armv.o] is 3308 bytes) Subsections have been available in binutils since 2004 at least, so they should not cause any issues with older toolchains. So use the above to implement the macros mov_l, adr_l, adrm_l (using ldm to load multiple literals at once), ldr_l and str_l, all of which will use movw/movt pairs on v7 and later CPUs, and use PC-relative literals otherwise. Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/assembler.h | 70 ++++++++++++++++++++ 1 file changed, 70 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index ad301f107dd2..cedf59a7f853 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -518,4 +518,74 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) #endif .endm +#ifdef CONFIG_THUMB2_KERNEL +#define ARM_PC_BIAS 4 +#else +#define ARM_PC_BIAS 8 +#endif + + .macro __adldst_l, op, reg, sym, tmp + .if __LINUX_ARM_ARCH__ < 7 + ldr \tmp, 111f + .subsection 1 + .align 2 +111: .long \sym - (222f + ARM_PC_BIAS) + .previous + .else + movw \tmp, #:lower16:\sym - (222f + ARM_PC_BIAS) + movt \tmp, #:upper16:\sym - (222f + ARM_PC_BIAS) + .endif +222:; .ifc \op, add + add \reg, \tmp, pc + .elseif CONFIG_THUMB2_KERNEL == 1 + add \tmp, \tmp, pc + \op \reg, [\tmp] + .else + \op \reg, [pc, \tmp] + .endif + .endm + + /* + * mov_l - move a constant value or [relocated] address into a register + */ + .macro mov_l, dst:req, imm:req + .if __LINUX_ARM_ARCH__ < 7 + ldr \dst, =\imm + .else + movw \dst, #:lower16:\imm + movt \dst, #:upper16:\imm + .endif + .endm + + /* + * adr_l - adr pseudo-op with unlimited range + * + * @dst: destination register + * @sym: name of the symbol + */ + .macro adr_l, dst:req, sym:req + __adldst_l add, \dst, \sym, \dst + .endm + + /* + * ldr_l - ldr pseudo-op with unlimited range + * + * @dst: destination register + * @sym: name of the symbol + */ + .macro ldr_l, dst:req, sym:req + __adldst_l ldr, \dst, \sym, \dst + .endm + + /* + * str_l - str pseudo-op with unlimited range + * + * @src: source register + * @sym: name of the symbol + * @tmp: mandatory scratch register + */ + .macro str_l, src:req, sym:req, tmp:req + __adldst_l str, \src, \sym, \tmp + .endm + #endif /* __ASM_ASSEMBLER_H__ */