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[209.132.180.67]) by mx.google.com with ESMTP id j61si92183plb.86.2017.03.27.02.50.35; Mon, 27 Mar 2017 02:50:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752845AbdC0Jtv (ORCPT + 4 others); Mon, 27 Mar 2017 05:49:51 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:63009 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752753AbdC0JsP (ORCPT ); Mon, 27 Mar 2017 05:48:15 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2R9kL1r001324; Mon, 27 Mar 2017 04:46:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1490607981; bh=ILIn1IP9xzL4el7VZScAb5AQTIFz+bg4FlNpLcvgSFw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I5YLYUVBaE4kcFyFKcysKv7ED/sZ92ylgw+rDutsYA0FMt8CjmJzkdel+TrvsHPae YiWK7LkazJB4Y5z9LNLu28y7uMai9/JWNkPm69JNACbeQpJzDjKgiCwpDmmNF7Ty9h XRQhovHY+MOqYaqefa+FeDuQOXdxXC6vA56HFY0s= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2R9kG6k024477; Mon, 27 Mar 2017 04:46:16 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 27 Mar 2017 04:46:15 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2R9jQIh012055; Mon, 27 Mar 2017 04:46:13 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , , Subject: [PATCH v5 13/24] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode Date: Mon, 27 Mar 2017 15:15:09 +0530 Message-ID: <20170327094520.3129-14-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170327094520.3129-1-kishon@ti.com> References: <20170327094520.3129-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add device tree binding documentation for pci dra7xx EP mode. Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/ti-pci.txt | 37 +++++++++++++++++++----- 1 file changed, 30 insertions(+), 7 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 60e25161f351..190828a5f32a 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -1,17 +1,22 @@ TI PCI Controllers PCIe Designware Controller - - compatible: Should be "ti,dra7-pcie"" - - reg : Two register ranges as listed in the reg-names property - - reg-names : The first entry must be "ti-conf" for the TI specific registers - The second entry must be "rc-dbics" for the designware pcie - registers - The third entry must be "config" for the PCIe configuration space + - compatible: Should be "ti,dra7-pcie" for RC + Should be "ti,dra7-pcie-ep" for EP - phys : list of PHY specifiers (used by generic PHY framework) - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the number of PHYs as specified in *phys* property. - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. + - num-lanes as specified in ../designware-pcie.txt + +HOST MODE +========= + - reg : Two register ranges as listed in the reg-names property + - reg-names : The first entry must be "ti-conf" for the TI specific registers + The second entry must be "rc-dbics" for the designware pcie + registers + The third entry must be "config" for the PCIe configuration space - interrupts : Two interrupt entries must be specified. The first one is for main interrupt line and the second for MSI interrupt line. - #address-cells, @@ -19,13 +24,31 @@ PCIe Designware Controller #interrupt-cells, device_type, ranges, - num-lanes, interrupt-map-mask, interrupt-map : as specified in ../designware-pcie.txt +DEVICE MODE +=========== + - reg : Four register ranges as listed in the reg-names property + - reg-names : "ti-conf" for the TI specific registers + "ep_dbics" for the standard configuration registers as + they are locally accessed within the DIF CS space + "ep_dbics2" for the standard configuration registers as + they are locally accessed within the DIF CS2 space + "addr_space" used to map remote RC address space + - interrupts : one interrupt entries must be specified for main interrupt. + - num-ib-windows : number of inbound address translation windows + - num-ob-windows : number of outbound address translation windows + Optional Property: - gpios : Should be added if a gpio line is required to drive PERST# line +NOTE: Two dt nodes may be added for each PCI controller; one for host +mode and another for device mode. So in order for PCI to +work in host mode, EP mode dt node should be disabled and in order to PCI to +work in EP mode, host mode dt node should be disabled. And host mode and EP +mode are mutually exclusive. + Example: axi { compatible = "simple-bus";