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[209.132.180.67]) by mx.google.com with ESMTP id u20si16248948plj.268.2017.01.23.09.25.14; Mon, 23 Jan 2017 09:25:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751136AbdAWRZM (ORCPT + 4 others); Mon, 23 Jan 2017 12:25:12 -0500 Received: from mail-wm0-f51.google.com ([74.125.82.51]:35985 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751397AbdAWRZK (ORCPT ); Mon, 23 Jan 2017 12:25:10 -0500 Received: by mail-wm0-f51.google.com with SMTP id c85so143293960wmi.1 for ; Mon, 23 Jan 2017 09:25:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zqlx2L9FqIkb80KY+NzpHNmM4rVVILFSS4Q0xwecWWM=; b=UdTGMdFxJink4qvEmquvIFEEX3talmrIyowJ+14XGQ86fmwmx3tjU1/k/KK/GXjkIJ by6Ez93mCXW+EmrptquPJoebnGCKn35i/pTWW9VD3kpz0J9Jk/8E9M2ws37X3u9VFzx6 7lX5RWmJfuVhV2PuhqngmCLkRA1bol6z+QW8v7BNGXWQMMQFQ0I1BM2ZYhRMRBYof/HX zjMDJv3tuBi8dA0ZhpXJKMHFGYsedgqUnefHN7scATB5PcAwMoDU/Qnprcm9AFoMDNez yp+Uuc4MVQ6sLxD8Tft553NVNuYT1bJ5i0vQKY6HkFV5dQ2lvWXjk80/KmoN7kQR2I+T Uy+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zqlx2L9FqIkb80KY+NzpHNmM4rVVILFSS4Q0xwecWWM=; b=mx56l77P7Z4Ma3POFP75f1PW7Rbi/AlVtgje41gICbbWLyQEqInnNUzHOHU+rw67rD FUYtgyIouabustpFPvGE6nUI9ZjUbig4UuQa11P0PoD2trHGvVg4HcuIXOF1VeuDr82i 3vMETF7UU56i0kJ23pWYgvLu9yOAbdTeakFki6G7emPMp1Z/1R7dsIvfZcfvdDcBURqp UaouIQEpizvN7PlLDhjaG3lCMaHgSrQfwsBRxsqhdUkuKHCM5qwf0Um9JH06ZS9r3zAQ OOqESigVjUFHj5QmARomMpqkDbxybEEUC2U4cSTFikbTJpVEdqCkrkIBmT5W8hfMyTSD VUgw== X-Gm-Message-State: AIkVDXKCDllfKCIiMk8OxUi7FIRH++qi9+hWqZwnaET868kWToOFw+alYBJRYniG0lLSK5QR X-Received: by 10.28.134.67 with SMTP id i64mr14005019wmd.5.1485192304030; Mon, 23 Jan 2017 09:25:04 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id g71sm11328119wmc.9.2017.01.23.09.25.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jan 2017 09:25:03 -0800 (PST) From: Alexandre Bailon To: vinod.koul@intel.com Cc: dmaengine@vger.kernel.org, nsekhar@ti.com, khilman@baylibre.com, ptitiano@baylibre.com, tony@atomide.com, linux-omap@vger.kernel.org, b-liu@ti.com, sergei.shtylyov@cogentembedded.com, Alexandre Bailon Subject: [PATCH v4 3/5] dmaengine: cppi41: Move some constants to glue layer Date: Mon, 23 Jan 2017 18:24:50 +0100 Message-Id: <20170123172453.30224-4-abailon@baylibre.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170123172453.30224-1-abailon@baylibre.com> References: <20170123172453.30224-1-abailon@baylibre.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Some constants are defined and use by the driver whereas they are specifics to AM335x. Add new variables to the glue layer, initialize them with the constants, and use them in the driver. Signed-off-by: Alexandre Bailon --- drivers/dma/cppi41.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c index a6addc3..5a40653 100644 --- a/drivers/dma/cppi41.c +++ b/drivers/dma/cppi41.c @@ -68,7 +68,6 @@ #define QMGR_MEMCTRL_IDX_SH 16 #define QMGR_MEMCTRL_DESC_SH 8 -#define QMGR_NUM_PEND 5 #define QMGR_PEND(x) (0x90 + (x) * 4) #define QMGR_PENDING_SLOT_Q(x) (x / 32) @@ -138,6 +137,8 @@ struct cppi41_dd { const struct chan_queues *queues_rx; const struct chan_queues *queues_tx; struct chan_queues td_queue; + u16 first_completion_queue; + u16 qmgr_num_pend; struct list_head pending; /* Pending queued transfers */ spinlock_t lock; /* Lock for pending list */ @@ -146,7 +147,6 @@ struct cppi41_dd { unsigned int dma_tdfdq; }; -#define FIST_COMPLETION_QUEUE 93 static struct chan_queues am335x_usb_queues_tx[] = { /* USB0 ENDP 1 */ [ 0] = { .submit = 32, .complete = 93}, @@ -224,6 +224,8 @@ struct cppi_glue_infos { const struct chan_queues *queues_rx; const struct chan_queues *queues_tx; struct chan_queues td_queue; + u16 first_completion_queue; + u16 qmgr_num_pend; }; static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c) @@ -278,19 +280,21 @@ static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num) static irqreturn_t cppi41_irq(int irq, void *data) { struct cppi41_dd *cdd = data; + u16 first_completion_queue = cdd->first_completion_queue; + u16 qmgr_num_pend = cdd->qmgr_num_pend; struct cppi41_channel *c; int i; - for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND; + for (i = QMGR_PENDING_SLOT_Q(first_completion_queue); i < qmgr_num_pend; i++) { u32 val; u32 q_num; val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i)); - if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) { + if (i == QMGR_PENDING_SLOT_Q(first_completion_queue) && val) { u32 mask; /* set corresponding bit for completetion Q 93 */ - mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE); + mask = 1 << QMGR_PENDING_BIT_Q(first_completion_queue); /* not set all bits for queues less than Q 93 */ mask--; /* now invert and keep only Q 93+ set */ @@ -862,7 +866,7 @@ static int init_cppi41(struct device *dev, struct cppi41_dd *cdd) return -ENOMEM; cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE); - cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE); + cppi_writel(TOTAL_DESCS_NUM, cdd->qmgr_mem + QMGR_LRAM_SIZE); cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE); ret = init_descs(dev, cdd); @@ -945,6 +949,8 @@ static const struct cppi_glue_infos am335x_usb_infos = { .queues_rx = am335x_usb_queues_rx, .queues_tx = am335x_usb_queues_tx, .td_queue = { .submit = 31, .complete = 0 }, + .first_completion_queue = 93, + .qmgr_num_pend = 5, }; static const struct of_device_id cppi41_dma_ids[] = { @@ -1027,6 +1033,8 @@ static int cppi41_dma_probe(struct platform_device *pdev) cdd->queues_rx = glue_info->queues_rx; cdd->queues_tx = glue_info->queues_tx; cdd->td_queue = glue_info->td_queue; + cdd->qmgr_num_pend = glue_info->qmgr_num_pend; + cdd->first_completion_queue = glue_info->first_completion_queue; ret = init_cppi41(dev, cdd); if (ret)