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[209.132.180.67]) by mx.google.com with ESMTP id n8si3151340pgc.160.2017.01.19.02.37.57; Thu, 19 Jan 2017 02:37:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751929AbdASKhx (ORCPT + 4 others); Thu, 19 Jan 2017 05:37:53 -0500 Received: from mail-wm0-f41.google.com ([74.125.82.41]:35631 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751832AbdASKhs (ORCPT ); Thu, 19 Jan 2017 05:37:48 -0500 Received: by mail-wm0-f41.google.com with SMTP id r126so283674725wmr.0 for ; Thu, 19 Jan 2017 02:37:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zqlx2L9FqIkb80KY+NzpHNmM4rVVILFSS4Q0xwecWWM=; b=12fwVbutM4XSrnc7qRvVqDyk/XauuD/bMcuJf4NactHoz4WH8wJIF74RxaFJiOcUsw OS7xkUKqMkQOuz4ukF2/sIHwITDidAVch1KthLDj7Lw5XAsL8RMMVCo+4lVBPRP4T7z6 nc9LOKlpl+CyDKbVB3fivwV14Qu+gKb0gFaGpMlmepQ24Xtjkzvdhy9vrh6+cDnu5wOr l0qOIEMhlQarSm3x6TaUT91Gh5O34f2ftRIN6tsQ58DvcomMOahtTdL+guPzbU2lHnJa qH/nQNpIzr85QR5L9XXX7U5uvdUtIHxUtz7+d5BKceRerzEFLS2daNIfTnAs2M7b9JCh GKNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zqlx2L9FqIkb80KY+NzpHNmM4rVVILFSS4Q0xwecWWM=; b=thjV86hMQ7K2GXIMMKv+QJJ2Dj4/s/87x4rjuEAElqDO0Y8xnc5GMDjCfBytNBYCn/ YlCRG/qRoCunK0ecO2FH87P+iBrBzHgm+evlcbme7Jz8pUAZl44aiYT1WRZWMPTEykNE rPtOZb+SIT0DJX1TrWNJwVaYZWG/rXNEFCyspXXiMQ1UfRMKnOElXlnKTscJ0MoD09YO 5/UQeXoNPqN7tqq3AAxvhldbBpkHONo/4gXstWJz7YMY0XdY52ZjMv+OZPlqQXdbQ3N8 CIZzXvXmCTrhpW1ZYfEi5nvLQs6QYD/iiqTSDKDYyLTv6nrLBDuQtNnlt6CPN2fN/hSS qj1g== X-Gm-Message-State: AIkVDXIf8ZKXRn0Fh159uvIFV8VZ59agDdgs1XIjMS5j9NlFu+grQehvNSITPOz75+k9GWiK X-Received: by 10.223.177.134 with SMTP id q6mr6785522wra.83.1484822232459; Thu, 19 Jan 2017 02:37:12 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id c81sm11850470wmf.22.2017.01.19.02.37.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Jan 2017 02:37:11 -0800 (PST) From: Alexandre Bailon To: vinod.koul@intel.com Cc: dmaengine@vger.kernel.org, nsekhar@ti.com, khilman@baylibre.com, ptitiano@baylibre.com, tony@atomide.com, linux-omap@vger.kernel.org, b-liu@ti.com, sergei.shtylyov@cogentembedded.com, grygorii.strashko@ti.com, linux-usb@vger.kernel.org, Alexandre Bailon Subject: [PATCH v3 3/4] dmaengine: cppi41: Move some constants to glue layer Date: Thu, 19 Jan 2017 11:37:04 +0100 Message-Id: <20170119103705.13532-4-abailon@baylibre.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170119103705.13532-1-abailon@baylibre.com> References: <20170119103705.13532-1-abailon@baylibre.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Some constants are defined and use by the driver whereas they are specifics to AM335x. Add new variables to the glue layer, initialize them with the constants, and use them in the driver. Signed-off-by: Alexandre Bailon --- drivers/dma/cppi41.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c index a6addc3..5a40653 100644 --- a/drivers/dma/cppi41.c +++ b/drivers/dma/cppi41.c @@ -68,7 +68,6 @@ #define QMGR_MEMCTRL_IDX_SH 16 #define QMGR_MEMCTRL_DESC_SH 8 -#define QMGR_NUM_PEND 5 #define QMGR_PEND(x) (0x90 + (x) * 4) #define QMGR_PENDING_SLOT_Q(x) (x / 32) @@ -138,6 +137,8 @@ struct cppi41_dd { const struct chan_queues *queues_rx; const struct chan_queues *queues_tx; struct chan_queues td_queue; + u16 first_completion_queue; + u16 qmgr_num_pend; struct list_head pending; /* Pending queued transfers */ spinlock_t lock; /* Lock for pending list */ @@ -146,7 +147,6 @@ struct cppi41_dd { unsigned int dma_tdfdq; }; -#define FIST_COMPLETION_QUEUE 93 static struct chan_queues am335x_usb_queues_tx[] = { /* USB0 ENDP 1 */ [ 0] = { .submit = 32, .complete = 93}, @@ -224,6 +224,8 @@ struct cppi_glue_infos { const struct chan_queues *queues_rx; const struct chan_queues *queues_tx; struct chan_queues td_queue; + u16 first_completion_queue; + u16 qmgr_num_pend; }; static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c) @@ -278,19 +280,21 @@ static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num) static irqreturn_t cppi41_irq(int irq, void *data) { struct cppi41_dd *cdd = data; + u16 first_completion_queue = cdd->first_completion_queue; + u16 qmgr_num_pend = cdd->qmgr_num_pend; struct cppi41_channel *c; int i; - for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND; + for (i = QMGR_PENDING_SLOT_Q(first_completion_queue); i < qmgr_num_pend; i++) { u32 val; u32 q_num; val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i)); - if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) { + if (i == QMGR_PENDING_SLOT_Q(first_completion_queue) && val) { u32 mask; /* set corresponding bit for completetion Q 93 */ - mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE); + mask = 1 << QMGR_PENDING_BIT_Q(first_completion_queue); /* not set all bits for queues less than Q 93 */ mask--; /* now invert and keep only Q 93+ set */ @@ -862,7 +866,7 @@ static int init_cppi41(struct device *dev, struct cppi41_dd *cdd) return -ENOMEM; cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE); - cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE); + cppi_writel(TOTAL_DESCS_NUM, cdd->qmgr_mem + QMGR_LRAM_SIZE); cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE); ret = init_descs(dev, cdd); @@ -945,6 +949,8 @@ static const struct cppi_glue_infos am335x_usb_infos = { .queues_rx = am335x_usb_queues_rx, .queues_tx = am335x_usb_queues_tx, .td_queue = { .submit = 31, .complete = 0 }, + .first_completion_queue = 93, + .qmgr_num_pend = 5, }; static const struct of_device_id cppi41_dma_ids[] = { @@ -1027,6 +1033,8 @@ static int cppi41_dma_probe(struct platform_device *pdev) cdd->queues_rx = glue_info->queues_rx; cdd->queues_tx = glue_info->queues_tx; cdd->td_queue = glue_info->td_queue; + cdd->qmgr_num_pend = glue_info->qmgr_num_pend; + cdd->first_completion_queue = glue_info->first_completion_queue; ret = init_cppi41(dev, cdd); if (ret)