From patchwork Fri Nov 9 00:57:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Turquette X-Patchwork-Id: 12775 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CA1442420A for ; Fri, 9 Nov 2012 00:57:45 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 54DE0A195EC for ; Fri, 9 Nov 2012 00:57:45 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so4980783iej.11 for ; Thu, 08 Nov 2012 16:57:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :content-type:mime-version:content-transfer-encoding:to:from :in-reply-to:cc:references:message-id:user-agent:subject:date :x-originating-ip:x-gm-message-state; bh=rIW8bKPtjelcujmTpTIzc0umFu9guGIP/f3FSN1coEE=; b=O7RrnXsYZ3cRr1XIbx70+YtOIjsZdJxTJa5ZyWeaRl5qlTXP07z5qJcCRed9SZ+6U9 GySH++GSyuyvtg3LOxSVQ7wrL7FHQ1Yz2SLekFGLphKgC5l3WsLwHfGRLC6Q3ruAj4ZH b9tcZFGEMa86ByISv/il4rLUTmxw51rOwQGjWrsW6+R2vUUKoR/zDsukuSbfUP6sxbx0 wF7MCk3ybZxAgEVQkecWAwdCjdxYTD94SiReTlG545E65Ppk5nQ/O22ILEo/MMovox0Q 1X41tx6ljnAbI+23bYaeGr+m8US2yNUWo4tbUNHlcDdLyuZBAy2D8mNzNDuRDd3BZpqs 8tjQ== Received: by 10.42.57.10 with SMTP id b10mr8782728ich.54.1352422664781; Thu, 08 Nov 2012 16:57:44 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp454098igt; Thu, 8 Nov 2012 16:57:44 -0800 (PST) Received: by 10.60.172.48 with SMTP id az16mr6433867oec.64.1352422664348; Thu, 08 Nov 2012 16:57:44 -0800 (PST) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com. [192.94.94.40]) by mx.google.com with ESMTPS id r3si12610831oef.51.2012.11.08.16.57.44 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 08 Nov 2012 16:57:44 -0800 (PST) Received-SPF: pass (google.com: domain of mturquette@ti.com designates 192.94.94.40 as permitted sender) client-ip=192.94.94.40; Authentication-Results: mx.google.com; spf=pass (google.com: domain of mturquette@ti.com designates 192.94.94.40 as permitted sender) smtp.mail=mturquette@ti.com Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id qA90vhFC024563; Thu, 8 Nov 2012 18:57:43 -0600 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA90vh9w028063; Thu, 8 Nov 2012 18:57:43 -0600 Received: from localhost (10.188.36.112) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server (TLS) id 14.1.323.3; Thu, 8 Nov 2012 18:57:43 -0600 MIME-Version: 1.0 To: Paul Walmsley From: Mike Turquette In-Reply-To: CC: , , , References: <1352337181-29427-1-git-send-email-mturquette@ti.com> <1352337181-29427-15-git-send-email-mturquette@ti.com> Message-ID: <20121109005727.17381.5145@nucleus> User-Agent: alot/0.3.2+ Subject: Re: [PATCH 14/26] ARM: OMAP3: clock: Add 3xxx data using common struct clk Date: Thu, 8 Nov 2012 16:57:27 -0800 X-Originating-IP: [10.188.36.112] X-Gm-Message-State: ALoCoQmnJixmNdWMHNBc26wlUsEIYR1AyrlaJVQLjffPhBaa7ontrOPF4RhjlqeBX/uPNldFZ57S Quoting Paul Walmsley (2012-11-08 16:11:12) > On Thu, 8 Nov 2012, Paul Walmsley wrote: > > > On Thu, 8 Nov 2012, Paul Walmsley wrote: > > > > > Am seeing warnings during the disable-unused-clocks phase of the boot on > > > the OMAP3 test boards here. > > > > Similar problems during system suspend on 3530ES3 Beagle. Not sure > > what's causing these yet. At this point the clockdomain usecounts > > should be accurate. > > Here's a redacted debugging log for these cases. The suspend events start > around the 30 second mark. > > One observation is that dpll4_m5x2_ck and dpll4_m6x2_ck are never enabled. > The tracebacks occur when something in the suspend path tries to disable > those clocks. Hi Paul, My instrumentation shows that dpll4_ck & dpll4_m2x2_ck are triggering the WARNs: [ 25.214599] _clkdm_clk_hwmod_disable: dpll4_m2x2_ck [ 25.214599] ------------[ cut here ]------------ [ 25.214660] WARNING: at arch/arm/mach-omap2/clockdomain.c:967 _clkdm_clk_hwmod_disable+0xd0/0x118() ... [ 25.215209] _clkdm_clk_hwmod_disable: dpll4_ck [ 25.215209] ------------[ cut here ]------------ [ 25.215240] WARNING: at arch/arm/mach-omap2/clockdomain.c:967 _clkdm_clk_hwmod_disable+0xd0/0x118() Patch that give that information: Regards, Mike > > > - Paul > > [ 0.135528] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 0.135559] clockdomain: dpll4_clkdm: enabled > [ 0.135589] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck > [ 0.135681] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck > [ 0.135711] clockdomain: dpll4_clkdm: disabled > [ 0.135772] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 0.135803] clockdomain: dpll4_clkdm: enabled > [ 0.135833] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 0.135894] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck > [ 0.135925] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck > [ 0.135955] clockdomain: dpll4_clkdm: disabled > [ 0.135986] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 0.136016] clockdomain: dpll4_clkdm: enabled > [ 0.136047] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 0.136138] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck > [ 0.136169] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck > [ 0.136169] clockdomain: dpll4_clkdm: disabled > [ 0.136260] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 0.136291] clockdomain: dpll4_clkdm: enabled > [ 0.136322] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 0.140594] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck > [ 0.140686] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck > [ 0.140838] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck > [ 0.140930] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck > [ 0.141479] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck > [ 0.141571] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck > [ 0.141601] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck > [ 0.141662] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck > [ 0.141693] enabling clkdm dpll4_clkdm during enable of clk dpll4_m4x2_ck > [ 0.141784] disabling clkdm dpll4_clkdm during disable of clk dpll4_m4x2_ck > [ 0.141815] enabling clkdm dpll4_clkdm during enable of clk dpll4_m3x2_ck > [ 0.141876] disabling clkdm dpll4_clkdm during disable of clk dpll4_m3x2_ck > [ 3.399200] disabling clkdm dpll4_clkdm during disable of clk dpll4_m6x2_ck > [ 3.417694] [] (unwind_backtrace+0x0/0xf0) from [] (warn_slowpath_common+0x4c/0x64) > [ 3.445251] ---[ end trace 72e2d7bdcf98ea8b ]--- > [ 3.450134] disabling clkdm dpll4_clkdm during disable of clk dpll4_m5x2_ck > [ 3.453918] clockdomain: dpll4_clkdm: disabled > [ 3.477569] [] (unwind_backtrace+0x0/0xf0) from [] (warn_slowpath_common+0x4c/0x64) > [ 3.505096] ---[ end trace 72e2d7bdcf98ea8c ]--- > [ 3.531280] [] (unwind_backtrace+0x0/0xf0) from [] (warn_slowpath_common+0x4c/0x64) > [ 3.558807] ---[ end trace 72e2d7bdcf98ea8d ]--- > [ 38.999145] disabling clkdm dpll4_clkdm during disable of clk dpll4_m2x2_ck > [ 38.999267] [] (unwind_backtrace+0x0/0xf0) from [] (warn_slowpath_common+0x4c/0x64) > [ 38.999816] ---[ end trace 72e2d7bdcf98ea8e ]--- > [ 38.999816] disabling clkdm dpll4_clkdm during disable of clk dpll4_ck > [ 38.999908] [] (unwind_backtrace+0x0/0xf0) from [] (warn_slowpath_common+0x4c/0x64) > [ 39.000366] ---[ end trace 72e2d7bdcf98ea8f ]--- > [ 42.169647] enabling clkdm dpll4_clkdm during enable of clk dpll4_ck > [ 42.169647] clockdomain: dpll4_clkdm: enabled > [ 42.169677] enabling clkdm dpll4_clkdm during enable of clk dpll4_m2x2_ck > [ 45.730346] [] (unwind_backtrace+0x0/0xf0) from [] (warn_slowpath_common+0x4c/0x64) > [ 45.795654] ---[ end trace 72e2d7bdcf98ea90 ]--- diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 64e5046..a9d5965 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -947,7 +947,8 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) return 0; } -static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) +static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm, + struct clk *clk) { unsigned long flags; @@ -957,6 +958,9 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) spin_lock_irqsave(&clkdm->lock, flags); if (atomic_read(&clkdm->usecount) == 0) { + if (clk) + pr_err("%s: %s\n", __func__, __clk_get_name(clk)); + spin_unlock_irqrestore(&clkdm->lock, flags); WARN_ON(1); /* underflow */ return -ERANGE; @@ -1026,7 +1030,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) if (!clk) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + return _clkdm_clk_hwmod_disable(clkdm, clk); } /** @@ -1089,6 +1093,6 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) if (!oh) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + return _clkdm_clk_hwmod_disable(clkdm, NULL); }