From patchwork Thu Apr 4 08:11:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 161762 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1297816jan; Thu, 4 Apr 2019 01:12:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqw1cs/ry3Djggo+0x5IiV0qqEh7nKW6kcdnPGK/iXlDr6Ce7V5BNosGeBQpKJMkMai65ssl X-Received: by 2002:a63:5858:: with SMTP id i24mr4473378pgm.222.1554365551980; Thu, 04 Apr 2019 01:12:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554365551; cv=none; d=google.com; s=arc-20160816; b=q81PN8xtJ31TXUdn60QwD+qCYI8pU1MaFxq78XH1rjX+gnAfNkvYDEBbqRtspE/eeP vQibMYlAc0BgNQrklWOUyZkMPNtM/gm25faPdaT8EEcG9skwWmAZY83A9WuSGpYhj/NA e2o7i07on0rkJkXeLYyio6eKalC+oJkYFGRUKw+EC343CBZha9Z8/Ze1BUgSZjfV+PFy Y65F1sGQUtDQ0HimqzaA0DC44BalP93cYXCzxJ8dnhutintkyGoPyxi6jjUER+opTS7D k2zXRVnFNKsFlVOm/inhPwzAnQ6u/yU5lzHvoBu3v7Y1ugTpNLIXzqDo+I4A+O4TVL3e 5Mlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TFvauUWsWvA21ez6hWIFoAZOdX/CAGXhrmUlNUztKXU=; b=SERB5jyLWpgrA9GfwN+HIfNkbg8VJNJQNywGsMri+e5ipYQsGubInJ1XErD0R2PjOB gMIFVpBKjYJ3hkca0Fd2dCQ9UEV1qKDAawDNC60PXoUsdPvMQ9BMSP23wDMiiVakn1Zd AezEPcJVnM1IQvLWO+2C1qf8A9/wWpevy8RY+S2ZgWYrUMFxSH1Co5Js+tLD9WWrL6vt YyfZ/ecZgzEHqyYeSen/abm8MNxu7GxeUXBL662tFrIGI+ZP16Lrl3pMHX/8RWpBYbg8 y2PojGYATn51cjFg7xG2wkkleMzAcyrAVSPuFbVN0fhQ1cSVsbud4gzqf/oER66q2pE0 SrAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Z24GdO1l; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m12si7767545pgv.586.2019.04.04.01.12.31; Thu, 04 Apr 2019 01:12:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Z24GdO1l; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727447AbfDDIMb (ORCPT + 5 others); Thu, 4 Apr 2019 04:12:31 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:45412 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725914AbfDDIMb (ORCPT ); Thu, 4 Apr 2019 04:12:31 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x348CRlf057260; Thu, 4 Apr 2019 03:12:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1554365547; bh=TFvauUWsWvA21ez6hWIFoAZOdX/CAGXhrmUlNUztKXU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Z24GdO1lsIsuMJlvjKUraOw9eogp1KxszBGR9HljCr1gmysoYOwveVrVeXO9CrZnp 6w39o5SkLdBGJWdMwbwt5igDn++BIRl4ARVBZd0TQy4ZZcNSnCt5MNA0PPVc+KfWJ3 GlFKOmQMZKw2iZTzDzReXVray3D310QLS9cJJjVw= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x348CRkR004977 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 4 Apr 2019 03:12:27 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 4 Apr 2019 03:12:25 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 4 Apr 2019 03:12:25 -0500 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x348C8GD093305; Thu, 4 Apr 2019 03:12:24 -0500 From: Tero Kristo To: , , , CC: , Eric Ruei Subject: [PATCH 6/6] clk: ti: am43xx: drop idlest polling from gfx clkctrl clock Date: Thu, 4 Apr 2019 11:11:07 +0300 Message-ID: <1554365467-1325-7-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1554365467-1325-1-git-send-email-t-kristo@ti.com> References: <1554365467-1325-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Eric Ruei The GFX modules on AM43xx SoCs have a hardreset line and are controlled by a GFX reset line. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for the GFX clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to the GFX clkctrl clock so that these module status checks are skipped. Signed-off-by: Eric Ruei Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-43xx-compat.c | 2 +- drivers/clk/ti/clk-43xx.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/clk/ti/clk-43xx-compat.c b/drivers/clk/ti/clk-43xx-compat.c index 5130398..ac8117d 100644 --- a/drivers/clk/ti/clk-43xx-compat.c +++ b/drivers/clk/ti/clk-43xx-compat.c @@ -65,7 +65,7 @@ }; static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = { - { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, + { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" }, { 0 }, }; diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 2782d91..9882a9b 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -73,7 +73,7 @@ }; static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = { - { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, + { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" }, { 0 }, };