From patchwork Mon Feb 26 15:10:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 129685 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp306100lja; Mon, 26 Feb 2018 07:10:54 -0800 (PST) X-Google-Smtp-Source: AH8x2279jnopQjmSBLA+wMoDC30KmcWKcztic9V1+kgqWd66KJLmzfFvkqtP/kpi94cfJWzI2EUk X-Received: by 10.101.96.212 with SMTP id r20mr8697251pgv.139.1519657854299; Mon, 26 Feb 2018 07:10:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657854; cv=none; d=google.com; s=arc-20160816; b=T6tJy5TCQEvCI2B//kS/mXC9wfJi8rbk3Bjl0B4HriHb5EGZ3Mc3cmZXnJF4s2Ujxz LQM+2Pq1UAZ4dAE3+0HDfZ/qEbXZ8oMhjClTfmyzcEA+F2wAmgFhFgLsldHuAcP1QWCu cYVYTiNsRUW7thkvm3oGucVf/T35XHbnNwu5+W4cIg8hk7jlZUT/2Fa1FFBCgAQdfTVW CJDxh3tB1gxCt/TQAcOdODkNsh7t8H6o7QFpscL7MhPo9STaBw22jRzedi2LSLZO+R3R Wn+bCB2Et1rzfe3GfEnLv7lfg8LKR+1gtvI1ufuSxIn/E87Z7a6cBtm+jHtDSbAj+dc8 yGFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=4bxdkSx/a7GIZnIx5dgOqQHTyeA6zCaHzw2Rg7HqpRA=; b=cXme3SkCzYc6R7JdExjj8VCoPLsCH76pyE+iOJR7w6QUJvER4bOmSToysbGpV/MxhY dVStYeBeoqplIXsk94Kyhsv8P/ToRz7IlfirKxLHShwl+Ro05oy0bcRi7Xs6J0WZ9M+Q Z3I/K3AQwvV6SH+VHjGqefeK/u3APPqK98RtbRzirFy8lCfQ8fzqH98v3njeVxfP7hwQ vvWewZZX/TsmnJSLv1ISVh35sVWMFPsrvqUHC2UE3nogc8KIk8fBIP+PRvZJTPPi9sQd vYNVDktm0qivlkblzfjnpOMqvqamtUmCFK2iWH6CA3AXD86E2ColnuGUOE2SX0Uvh3Ha Uu4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=JQu0K3P6; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u76si5641447pgc.218.2018.02.26.07.10.54; Mon, 26 Feb 2018 07:10:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=JQu0K3P6; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754024AbeBZPKx (ORCPT + 5 others); Mon, 26 Feb 2018 10:10:53 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:21126 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753881AbeBZPKw (ORCPT ); Mon, 26 Feb 2018 10:10:52 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w1QFAnqE027555; Mon, 26 Feb 2018 09:10:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1519657849; bh=wp9s29PGUBsfxWd12DShNQmPvpS6mWy5sHC/uzrVZb8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JQu0K3P6iSJ2t4xWMiKcOQPKCCKzybF6ImATkPa43pWAjUcHmwtsh2nsjs1yWTp0p 6IuNofyGtj3uhIM5rU9gn+Xe4LVBdUKsa/wuMwibPUBP8Q5AYNPN11jWJhKEV5+3+Y 6la9hIAEWgR2m3cU0sS1VU9agqMfsfPyaFiW1RX8= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1QFAn6K029357; Mon, 26 Feb 2018 09:10:49 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 26 Feb 2018 09:10:49 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 26 Feb 2018 09:10:49 -0600 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1QFAgEl005932; Mon, 26 Feb 2018 09:10:47 -0600 From: Tero Kristo To: , , CC: , , Subject: [PATCH 2/3] clk: ti: am33xx: add set-rate-parent support for display clkctrl clock Date: Mon, 26 Feb 2018 17:10:11 +0200 Message-ID: <1519657812-15605-3-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519657812-15605-1-git-send-email-t-kristo@ti.com> References: <1519657812-15605-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Display driver assumes it can use clk_set_rate for the display clock via set-rate-parent mechanism, so add the flag for this to it. Signed-off-by: Tero Kristo Reported-by: Jyri Sarha --- drivers/clk/ti/clk-33xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index 612491a..12e0a2d 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -45,7 +45,7 @@ static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = { { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" }, - { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP, "lcd_gclk", "lcdc_clkdm" }, + { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" }, { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" }, { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },