From patchwork Mon Jun 20 08:43:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 70414 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp1404962qgy; Mon, 20 Jun 2016 01:50:47 -0700 (PDT) X-Received: by 10.66.22.134 with SMTP id d6mr20863227paf.35.1466412644841; Mon, 20 Jun 2016 01:50:44 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d186si32054245pfc.62.2016.06.20.01.50.44; Mon, 20 Jun 2016 01:50:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753561AbcFTIug (ORCPT + 3 others); Mon, 20 Jun 2016 04:50:36 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:60527 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753516AbcFTIu2 (ORCPT ); Mon, 20 Jun 2016 04:50:28 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u5K8hljb015522; Mon, 20 Jun 2016 03:43:47 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u5K8iP3H015761; Mon, 20 Jun 2016 03:44:25 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Mon, 20 Jun 2016 03:44:25 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u5K8ho6Y025602; Mon, 20 Jun 2016 03:44:21 -0500 From: Keerthy To: , , CC: , , , , , , , , Dave Gerlach Subject: [PATCH 8/9] regulator: tps65218: do not disable DCDC3 during poweroff on broken PMICs Date: Mon, 20 Jun 2016 14:13:37 +0530 Message-ID: <1466412218-5906-9-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466412218-5906-1-git-send-email-j-keerthy@ti.com> References: <1466412218-5906-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Tero Kristo Some versions of tps65218 do not seem to support poweroff modes properly if DCDC3 regulator is shut-down. Thus, keep it enabled even during poweroff if the version info matches the broken silicon revision. Signed-off-by: Tero Kristo Signed-off-by: Dave Gerlach Signed-off-by: Keerthy --- drivers/regulator/tps65218-regulator.c | 8 ++++++++ include/linux/mfd/tps65218.h | 5 +++++ 2 files changed, 13 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/regulator/tps65218-regulator.c b/drivers/regulator/tps65218-regulator.c index d1e631d..eb0f5b1 100644 --- a/drivers/regulator/tps65218-regulator.c +++ b/drivers/regulator/tps65218-regulator.c @@ -180,6 +180,14 @@ static int tps65218_pmic_set_suspend_disable(struct regulator_dev *dev) if (rid < TPS65218_DCDC_1 || rid > TPS65218_LDO_1) return -EINVAL; + /* + * Certain revisions of TPS65218 will need to have DCDC3 regulator + * enabled always, otherwise an immediate system reboot will occur + * during poweroff. + */ + if (rid == TPS65218_DCDC_3 && tps->rev == TPS65218_REV_2_1) + return 0; + if (!tps->info[rid]->strobe) { if (rid == TPS65218_DCDC_3) tps->info[rid]->strobe = 3; diff --git a/include/linux/mfd/tps65218.h b/include/linux/mfd/tps65218.h index 85e464e..d1db952 100644 --- a/include/linux/mfd/tps65218.h +++ b/include/linux/mfd/tps65218.h @@ -63,6 +63,11 @@ #define TPS65218_CHIPID_CHIP_MASK 0xF8 #define TPS65218_CHIPID_REV_MASK 0x07 +#define TPS65218_REV_1_0 0x0 +#define TPS65218_REV_1_1 0x1 +#define TPS65218_REV_2_0 0x2 +#define TPS65218_REV_2_1 0x3 + #define TPS65218_INT1_VPRG BIT(5) #define TPS65218_INT1_AC BIT(4) #define TPS65218_INT1_PB BIT(3)