From patchwork Thu Mar 3 11:28:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 63461 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp2887957lbc; Thu, 3 Mar 2016 03:28:26 -0800 (PST) X-Received: by 10.66.190.168 with SMTP id gr8mr2874965pac.23.1457004506660; Thu, 03 Mar 2016 03:28:26 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id rx5si4011367pab.151.2016.03.03.03.28.26; Thu, 03 Mar 2016 03:28:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753121AbcCCL2Z (ORCPT + 3 others); Thu, 3 Mar 2016 06:28:25 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:40454 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752741AbcCCL2Z (ORCPT ); Thu, 3 Mar 2016 06:28:25 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u23BSNQi002726; Thu, 3 Mar 2016 05:28:23 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u23BSNI1027758; Thu, 3 Mar 2016 05:28:23 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Thu, 3 Mar 2016 05:28:22 -0600 Received: from lta0400828d.emea.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u23BSLQH027436; Thu, 3 Mar 2016 05:28:22 -0600 From: Roger Quadros To: CC: , , Roger Quadros Subject: [PATCH] ARM: dts: dra7-evm: Fix comment about NAND configuration Date: Thu, 3 Mar 2016 13:28:20 +0200 Message-ID: <1457004500-10739-1-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.5.0 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The switch configuration for NAND is actually the other way round. Also mention ON/OFF states as that is more natural to understand (without the help of schematics) when compared to HIGH/LOW. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra7-evm.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index d9b8723..3410772 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -254,8 +254,9 @@ nand_flash_x16: nand_flash_x16 { /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch * So NAND flash requires following switch settings: - * SW5.9 (GPMC_WPN) = LOW - * SW5.1 (NAND_BOOTn) = HIGH */ + * SW5.1 (NAND_BOOTn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */