From patchwork Tue Feb 23 16:37:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 62730 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp1927075lbl; Tue, 23 Feb 2016 08:37:43 -0800 (PST) X-Received: by 10.98.86.139 with SMTP id h11mr47512007pfj.105.1456245463806; Tue, 23 Feb 2016 08:37:43 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id gj3si48189870pac.243.2016.02.23.08.37.43; Tue, 23 Feb 2016 08:37:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753620AbcBWQhk (ORCPT + 3 others); Tue, 23 Feb 2016 11:37:40 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:60616 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753496AbcBWQhh (ORCPT ); Tue, 23 Feb 2016 11:37:37 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u1NGbX5g022343; Tue, 23 Feb 2016 10:37:33 -0600 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1NGbX9A007654; Tue, 23 Feb 2016 10:37:33 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Tue, 23 Feb 2016 10:37:33 -0600 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1NGbQcQ016993; Tue, 23 Feb 2016 10:37:30 -0600 From: Roger Quadros To: CC: , , , , , , , , Roger Quadros Subject: [PATCH v7 1/9] ARM: dts: dra7: Fix NAND device nodes. Date: Tue, 23 Feb 2016 18:37:17 +0200 Message-ID: <1456245445-31824-2-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1456245445-31824-1-git-send-email-rogerq@ti.com> References: <1456245445-31824-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra7-evm.dts | 6 +++++- arch/arm/boot/dts/dra7.dtsi | 2 ++ arch/arm/boot/dts/dra72-evm.dts | 6 +++++- 3 files changed, 12 insertions(+), 2 deletions(-) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index cfc24e5..28ae95e 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -741,9 +741,13 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nand_flash_x16>; - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c4d9175..51ddc98 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1438,6 +1438,8 @@ gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 00b1200..6cf211b 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -492,13 +492,17 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nand_default>; - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { /* To use NAND, DIP switch SW5 must be set like so: * SW5.1 (NAND_SELn) = ON (LOW) * SW5.9 (GPMC_WPN) = OFF (HIGH) */ + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>;