From patchwork Fri Dec 18 13:58:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 58668 Delivered-To: patch@linaro.org Received: by 10.112.89.199 with SMTP id bq7csp1041960lbb; Fri, 18 Dec 2015 05:58:23 -0800 (PST) X-Received: by 10.98.73.78 with SMTP id w75mr5429857pfa.138.1450447095747; Fri, 18 Dec 2015 05:58:15 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id va5si24205142pac.165.2015.12.18.05.58.15; Fri, 18 Dec 2015 05:58:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932587AbbLRN6A (ORCPT + 3 others); Fri, 18 Dec 2015 08:58:00 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:35721 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932468AbbLRN57 (ORCPT ); Fri, 18 Dec 2015 08:57:59 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id tBIDvZW4012733; Fri, 18 Dec 2015 07:57:35 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id tBIDvZQ5030548; Fri, 18 Dec 2015 07:57:35 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Fri, 18 Dec 2015 07:57:34 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id tBIDvKUG021403; Fri, 18 Dec 2015 07:57:33 -0600 From: Tero Kristo To: , , , , CC: Subject: [RFC 5/9] dt-bindings: clk: ti: Document module clock type Date: Fri, 18 Dec 2015 15:58:57 +0200 Message-ID: <1450447141-29936-6-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1450447141-29936-1-git-send-email-t-kristo@ti.com> References: <1450447141-29936-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Document the new TI module clock type, which is intended to replace the internal clock control handling within omap_hwmod. Module clock is effectively a gate clock controlling both interface and functional clocks for a single hardware IP block. Signed-off-by: Tero Kristo --- .../devicetree/bindings/clock/ti/module.txt | 57 ++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/module.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/ti/module.txt b/Documentation/devicetree/bindings/clock/ti/module.txt new file mode 100644 index 0000000..a5f70f2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/module.txt @@ -0,0 +1,57 @@ +Binding for Texas Instruments module clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. This clock is +quite much similar to the basic gate-clock [2], however, internally +it controls an OMAP module clock, which effectively handles +both interface and functional clocks for a single module. In some +cases, support for mux clock [3] is composited to the same clock node, +currently only needed for proper support of timer module clocks. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/gate.txt +[3] Documentation/devicetree/bindings/clock/ti/mux.txt + +Required properties: +- compatible : shall be one of: + "ti,omap4-mod-clock" - basic module clock, no gating supported + "ti,omap4-hw-mod-clock" - module clock with hardware gating support + "ti,omap4-sw-mod-clock" - module clock with software forced gating support + "ti,omap4-mux-mod-clock" - composite clock with mux and module clocks, no + gating supported + "ti,omap4-hw-mux-mod-clock" - composite clock with mux and module clocks, + with hardware gating + "ti,omap4-sw-mux-mod-clock" - composite clock with mux and module clocks, + with software forced gating + +- #clock-cells : from common clock binding; shall be set to 0 +- clocks : link to phandle of parent clock(s) +- reg : offset for register controlling adjustable gate and optional mux + +Optional properties: +- ti,bit-shift : bit shift for programming the clock mux, only needed for + the nodes of the mux variant + +Examples: + timer6_mod_ck: timer6_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mux-mod-clock"; + reg = <0x0570>; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + }; + + i2c1_mod_ck: i2c1_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-sw-mod-clock"; + reg = <0x14a0>; + clocks = <&func_96m_fclk>; + }; + + hsi_mod_ck: hsi_mod_ck { + #clock-cells = <0>; + compatible = "ti,omap4-hw-mod-clock"; + reg = <0x1338>; + clocks = <&hsi_fck>; + };