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[209.132.180.67]) by mx.google.com with ESMTP id e193si17094897ioe.131.2015.10.16.09.22.46; Fri, 16 Oct 2015 09:22:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932450AbbJPQWp (ORCPT + 5 others); Fri, 16 Oct 2015 12:22:45 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:53757 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932423AbbJPQWp (ORCPT ); Fri, 16 Oct 2015 12:22:45 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id t9GGMN4u020352; Fri, 16 Oct 2015 11:22:23 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t9GGMNUx028828; Fri, 16 Oct 2015 11:22:23 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Fri, 16 Oct 2015 11:22:23 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t9GGMMMI002493; Fri, 16 Oct 2015 11:22:23 -0500 From: Felipe Balbi To: Tony Lindgren CC: Linux OMAP Mailing List , Linux ARM Kernel Mailing List , Felipe Balbi Subject: [PATCH 11/11] arm: omap2: timer: limit hwmod usage to non-DT boots Date: Fri, 16 Oct 2015 11:22:10 -0500 Message-ID: <1445012530-14126-12-git-send-email-balbi@ti.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: <1445012530-14126-1-git-send-email-balbi@ti.com> References: <1445012530-14126-1-git-send-email-balbi@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: balbi@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.180 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , now that we have a working 32k clocksource driver, we can limit HWMOD usage to non-DT boots and rely on clocksource_of_init() every time we boot with DT. While at that, also make sure that we don't disable the 32-counter device so it gets probed by its driver. Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/timer.c | 33 +++++++++++++-------------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index d024b2bb5c4c..05c17eb2f2d9 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -183,7 +183,8 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id * of_get_property(np, "ti,timer-secure", NULL))) continue; - of_add_property(np, &device_disabled); + if (!of_device_is_compatible(np, "ti,omap-counter32k")) + of_add_property(np, &device_disabled); return np; } @@ -394,7 +395,6 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void) int ret; struct device_node *np = NULL; struct omap_hwmod *oh; - void __iomem *vbase; const char *oh_name = "counter_32k"; /* @@ -420,18 +420,6 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void) omap_hwmod_setup_one(oh_name); - if (np) { - vbase = of_iomap(np, 0); - of_node_put(np); - } else { - vbase = omap_hwmod_get_mpu_rt_va(oh); - } - - if (!vbase) { - pr_warn("%s: failed to get counter_32k resource\n", __func__); - return -ENXIO; - } - ret = omap_hwmod_enable(oh); if (ret) { pr_warn("%s: failed to enable counter_32k module (%d)\n", @@ -439,13 +427,18 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void) return ret; } - ret = omap_init_clocksource_32k(vbase); - if (ret) { - pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", - __func__, ret); - omap_hwmod_idle(oh); - } + if (!of_have_populated_dt()) { + void __iomem *vbase; + vbase = omap_hwmod_get_mpu_rt_va(oh); + + ret = omap_init_clocksource_32k(vbase); + if (ret) { + pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", + __func__, ret); + omap_hwmod_idle(oh); + } + } return ret; }