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[209.132.180.67]) by mx.google.com with ESMTP id tv2si20042739pac.119.2015.10.02.16.23.56; Fri, 02 Oct 2015 16:23:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751208AbbJBXXz (ORCPT + 7 others); Fri, 2 Oct 2015 19:23:55 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:35102 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750709AbbJBXXz (ORCPT ); Fri, 2 Oct 2015 19:23:55 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t92NNRB0030015; Fri, 2 Oct 2015 18:23:27 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t92NNRJ6026845; Fri, 2 Oct 2015 18:23:27 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Fri, 2 Oct 2015 18:23:27 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t92NNRdM023815; Fri, 2 Oct 2015 18:23:27 -0500 Received: from localhost (irmo.am.dhcp.ti.com [128.247.9.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id t92NNR919835; Fri, 2 Oct 2015 18:23:27 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: , , , , Suman Anna Subject: [REPOST PATCH 4/4] ARM: dts: DRA74x: Add IOMMU nodes for DSP2 Date: Fri, 2 Oct 2015 18:23:25 -0500 Message-ID: <1443828205-18706-5-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 2.6.0 In-Reply-To: <1443828205-18706-1-git-send-email-s-anna@ti.com> References: <1443828205-18706-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: s-anna@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The DRA74x family of SoCs have a second DSP, that also has two MMUs just like the DSP1 subsystem. Add the IOMMU nodes for this DSP2 subsystem in disabled state to the DRA74x specific DTS file, the nodes would need to be enabled appropriately in the respective board DTS files. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra74x.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index dfa29b7ba86a..2f7d313e91a0 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -81,6 +81,26 @@ dr_mode = "otg"; }; }; + + mmu0_dsp2: mmu@41501000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x41501000 0x100>; + interrupts = ; + ti,hwmods = "mmu0_dsp2"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x0>; + status = "disabled"; + }; + + mmu1_dsp2: mmu@41502000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x41502000 0x100>; + interrupts = ; + ti,hwmods = "mmu1_dsp2"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x1>; + status = "disabled"; + }; }; };