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[209.132.180.67]) by mx.google.com with ESMTP id i192si6114380ioe.47.2015.10.01.12.33.17; Thu, 01 Oct 2015 12:33:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754146AbbJATdQ (ORCPT + 5 others); Thu, 1 Oct 2015 15:33:16 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:56707 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751194AbbJATdK (ORCPT ); Thu, 1 Oct 2015 15:33:10 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t91JWh3C009146; Thu, 1 Oct 2015 14:32:44 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t91JWhsD008180; Thu, 1 Oct 2015 14:32:43 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Thu, 1 Oct 2015 14:32:43 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t91JWhCM023402; Thu, 1 Oct 2015 14:32:43 -0500 Received: from localhost (irmo.am.dhcp.ti.com [128.247.9.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id t91JWh902277; Thu, 1 Oct 2015 14:32:43 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , , Suman Anna Subject: [PATCH 3/4] ARM: dts: DRA7: Add timer12 node Date: Thu, 1 Oct 2015 14:32:39 -0500 Message-ID: <1443727960-32232-4-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 2.6.0 In-Reply-To: <1443727960-32232-1-git-send-email-s-anna@ti.com> References: <1443727960-32232-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: s-anna@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add the DT node for Timer12 present on DRA7 family of SoCs. Timer12 is present in PD_WKUPAON power domain, and has the same capabilities as the other timers, except for the fact that it serves as a secure timer on HS devices and is clocked only from the secure 32K clock. The node is marked disabled for now, and the kernel should refrain from using this secure timer on HS devices. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra7.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e289c706d27d..37d632dad576 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -762,6 +762,16 @@ ti,hwmods = "timer11"; }; + timer12: timer@4ae20000 { + compatible = "ti,omap5430-timer"; + reg = <0x4ae20000 0x80>; + interrupts = ; + ti,hwmods = "timer12"; + ti,timer-alwon; + ti,timer-secure; + status = "disabled"; + }; + timer13: timer@48828000 { compatible = "ti,omap5430-timer"; reg = <0x48828000 0x80>;