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[209.132.180.67]) by mx.google.com with ESMTP id i192si6114380ioe.47.2015.10.01.12.33.14; Thu, 01 Oct 2015 12:33:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753573AbbJATdN (ORCPT + 5 others); Thu, 1 Oct 2015 15:33:13 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:56708 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752261AbbJATdK (ORCPT ); Thu, 1 Oct 2015 15:33:10 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t91JWhGK009139; Thu, 1 Oct 2015 14:32:44 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t91JWhs1008180; Thu, 1 Oct 2015 14:32:43 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Thu, 1 Oct 2015 14:32:43 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t91JWhfo005441; Thu, 1 Oct 2015 14:32:43 -0500 Received: from localhost (irmo.am.dhcp.ti.com [128.247.9.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id t91JWg902273; Thu, 1 Oct 2015 14:32:42 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , , Suman Anna Subject: [PATCH 2/4] ARM: OMAP2+: timer: Remove secure timer for DRA7xx devices Date: Thu, 1 Oct 2015 14:32:38 -0500 Message-ID: <1443727960-32232-3-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 2.6.0 In-Reply-To: <1443727960-32232-1-git-send-email-s-anna@ti.com> References: <1443727960-32232-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: s-anna@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Timer 12 on DRA7 SoCs is reserved for secure usage on high-secure (HS) devices. The timer cannot be used by the kernel on HS devices, but is available on regular general purpose (GP) devices. This is similar to the behavior on OMAP3 devices, so extend the logic used in commit ad24bde8f102 ("ARM: OMAP3: Dynamically disable secure timer nodes for secure devices") to remove the secure timer on DRA7xx SoCs at run-time based on the SoC device type. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index a55655127ef2..1e346aa0a687 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -193,8 +193,8 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id * /** * omap_dmtimer_init - initialisation function when device tree is used * - * For secure OMAP3 devices, timers with device type "timer-secure" cannot - * be used by the kernel as they are reserved. Therefore, to prevent the + * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure" + * cannot be used by the kernel as they are reserved. Therefore, to prevent the * kernel registering these devices remove them dynamically from the device * tree on boot. */ @@ -202,7 +202,7 @@ static void __init omap_dmtimer_init(void) { struct device_node *np; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !soc_is_dra7xx()) return; /* If we are a secure device, remove any secure timer nodes */