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[209.132.180.67]) by mx.google.com with ESMTP id of4si7756pbc.79.2014.11.04.02.49.29 for ; Tue, 04 Nov 2014 02:49:30 -0800 (PST) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752845AbaKDKt2 (ORCPT + 4 others); Tue, 4 Nov 2014 05:49:28 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:60091 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752617AbaKDKt1 (ORCPT ); Tue, 4 Nov 2014 05:49:27 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id sA4AnGIk001906; Tue, 4 Nov 2014 04:49:16 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id sA4AnGvf017850; Tue, 4 Nov 2014 04:49:16 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Tue, 4 Nov 2014 04:49:15 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id sA4AmutS007794; Tue, 4 Nov 2014 04:49:11 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , Roger Quadros Subject: [PATCH v3 04/10] ARM: dts: dra72-evm: Add CAN support Date: Tue, 4 Nov 2014 12:48:48 +0200 Message-ID: <1415098134-26405-5-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415098134-26405-1-git-send-email-rogerq@ti.com> References: <1415098134-26405-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The board has 2 CAN ports but only the first one can be used. Enable the first CAN port. WAKEUP0 pin doesn't have INPUT enable bit so we just disable weak PULLs. The second CAN port cannot be used without hardware modification so we don't enable the second port. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra72-evm.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 4107428..a4b01ce 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -26,6 +26,22 @@ 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ >; }; + + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ + 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1_pins_sleep { + pinctrl-single,pins = < + 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ + 0x418 (MUX_MODE15) /* wakeup0.off */ + >; + }; }; &i2c1 { @@ -142,3 +158,10 @@ &uart1 { status = "okay"; }; + +&dcan1 { + status = "ok"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcan1_pins_default>; + pinctrl-1 = <&dcan1_pins_sleep>; +};