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[209.132.180.67]) by mx.google.com with ESMTP id h3si17687129pdr.74.2014.11.04.02.22.12 for ; Tue, 04 Nov 2014 02:22:13 -0800 (PST) Received-SPF: none (google.com: netdev-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752906AbaKDKWG (ORCPT + 3 others); Tue, 4 Nov 2014 05:22:06 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:60771 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752203AbaKDKWD (ORCPT ); Tue, 4 Nov 2014 05:22:03 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id sA4ALcOv014412; Tue, 4 Nov 2014 04:21:38 -0600 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id sA4ALcZN028890; Tue, 4 Nov 2014 04:21:38 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Tue, 4 Nov 2014 04:21:37 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id sA4ALEGF020969; Tue, 4 Nov 2014 04:21:34 -0600 From: Roger Quadros To: , CC: , , , , , , , , , , , , Roger Quadros Subject: [PATCH v3 5/8] net: can: c_can: Add support for START pulse in RAMINIT sequence Date: Tue, 4 Nov 2014 12:20:58 +0200 Message-ID: <1415096461-25576-6-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415096461-25576-1-git-send-email-rogerq@ti.com> References: <1415096461-25576-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: netdev@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Some SoCs e.g. (TI DRA7xx) need a START pulse to start the RAMINIT sequence i.e. START bit must be set and cleared before checking for the DONE bit status. Signed-off-by: Roger Quadros --- drivers/net/can/c_can/c_can_platform.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c index d0ce439..ef1f5ce 100644 --- a/drivers/net/can/c_can/c_can_platform.c +++ b/drivers/net/can/c_can/c_can_platform.c @@ -124,6 +124,12 @@ static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable) ctrl |= 1 << start_bit; regmap_write(raminit->syscon, raminit->reg, ctrl); + /* clear START bit if start pulse is needed */ + if (priv->drvdata->raminit_pulse) { + ctrl &= ~(1 << start_bit); + regmap_write(raminit->syscon, raminit->reg, ctrl); + } + ctrl |= 1 << done_bit; c_can_hw_raminit_wait_syscon(priv, mask, ctrl); }