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[209.132.180.67]) by mx.google.com with ESMTP id bs14si8943969pdb.173.2014.10.31.03.52.33 for ; Fri, 31 Oct 2014 03:52:34 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757898AbaJaKwd (ORCPT + 4 others); Fri, 31 Oct 2014 06:52:33 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:42804 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756393AbaJaKwc (ORCPT ); Fri, 31 Oct 2014 06:52:32 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s9VAqUMo022370; Fri, 31 Oct 2014 05:52:30 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9VAqUOD020843; Fri, 31 Oct 2014 05:52:30 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Fri, 31 Oct 2014 05:52:31 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9VAqSB6014274; Fri, 31 Oct 2014 05:52:28 -0500 From: Roger Quadros To: CC: , , , , Roger Quadros Subject: [PATCH] pinctrl: dra: dt-bindings: Fix output pull up/down Date: Fri, 31 Oct 2014 12:52:25 +0200 Message-ID: <1414752745-13696-1-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , For PIN_OUTPUT_PULLUP and PIN_OUTPUT_PULLDOWN we must not set the PULL_DIS bit which disables the PULLs. While at that get rid for the PULL_ENA defination. It is misleading as there is no PULL enable bit in the register. And a zero bit defination makes no sense. Fixes: 23d9cec07c58 (:pinctrl: dra: dt-bindings: Fix pull enable/disable") Signed-off-by: Roger Quadros --- include/dt-bindings/pinctrl/dra.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h index 3d33794..71098e4 100644 --- a/include/dt-bindings/pinctrl/dra.h +++ b/include/dt-bindings/pinctrl/dra.h @@ -30,7 +30,6 @@ #define MUX_MODE14 0xe #define MUX_MODE15 0xf -#define PULL_ENA (0 << 16) #define PULL_DIS (1 << 16) #define PULL_UP (1 << 17) #define INPUT_EN (1 << 18) @@ -40,12 +39,12 @@ /* Active pin states */ #define PIN_OUTPUT (0 | PULL_DIS) -#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) -#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN (0) #define PIN_INPUT (INPUT_EN | PULL_DIS) #define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) #endif