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[209.132.180.67]) by mx.google.com with ESMTP id fk2si25356202pdb.228.2014.09.15.14.16.12 for ; Mon, 15 Sep 2014 14:16:12 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754648AbaIOVQK (ORCPT + 5 others); Mon, 15 Sep 2014 17:16:10 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:49968 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754553AbaIOVQJ (ORCPT ); Mon, 15 Sep 2014 17:16:09 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s8FLFhe4018102; Mon, 15 Sep 2014 16:15:43 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8FLFhU6030648; Mon, 15 Sep 2014 16:15:43 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Mon, 15 Sep 2014 16:15:42 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8FLFgPc010596; Mon, 15 Sep 2014 16:15:42 -0500 From: Felipe Balbi To: Tony Lindgren CC: Jason Cooper , Linux OMAP Mailing List , Linux ARM Kernel Mailing List , Felipe Balbi Subject: [PATCH 8/9] irqchip: omap-intc: correct maximum number or MIR registers Date: Mon, 15 Sep 2014 16:15:08 -0500 Message-ID: <1410815709-462-9-git-send-email-balbi@ti.com> X-Mailer: git-send-email 2.0.1.563.g66f467c In-Reply-To: <1410815709-462-1-git-send-email-balbi@ti.com> References: <1410815709-462-1-git-send-email-balbi@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: balbi@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , maximum number of MIR register is 4, rather than 3. Fix that. Acked-by: Jason Cooper Signed-off-by: Felipe Balbi --- drivers/irqchip/irq-omap-intc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c index dfa2d9d..976d4c1 100644 --- a/drivers/irqchip/irq-omap-intc.c +++ b/drivers/irqchip/irq-omap-intc.c @@ -49,7 +49,7 @@ #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ #define INTCPS_NR_ILR_REGS 128 -#define INTCPS_NR_MIR_REGS 3 +#define INTCPS_NR_MIR_REGS 4 #define INTC_IDLE_FUNCIDLE (1 << 0) #define INTC_IDLE_TURBO (1 << 1)