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[209.132.180.67]) by mx.google.com with ESMTP id fk2si25356202pdb.228.2014.09.15.14.16.09 for ; Mon, 15 Sep 2014 14:16:10 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754629AbaIOVQI (ORCPT + 5 others); Mon, 15 Sep 2014 17:16:08 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:37401 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754364AbaIOVQE (ORCPT ); Mon, 15 Sep 2014 17:16:04 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s8FLFeHJ020443; Mon, 15 Sep 2014 16:15:40 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8FLFeCU030628; Mon, 15 Sep 2014 16:15:40 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Mon, 15 Sep 2014 16:15:40 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s8FLFeho010545; Mon, 15 Sep 2014 16:15:40 -0500 From: Felipe Balbi To: Tony Lindgren CC: Jason Cooper , Linux OMAP Mailing List , Linux ARM Kernel Mailing List , Felipe Balbi Subject: [PATCH 6/9] irqchip: omap-intc: enable IP protection Date: Mon, 15 Sep 2014 16:15:06 -0500 Message-ID: <1410815709-462-7-git-send-email-balbi@ti.com> X-Mailer: git-send-email 2.0.1.563.g66f467c In-Reply-To: <1410815709-462-1-git-send-email-balbi@ti.com> References: <1410815709-462-1-git-send-email-balbi@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: balbi@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , When PROTECTION bit in enabled in PROTECTION register, INTC's registers are only accessible from privileged mode. Acked-by: Jason Cooper Signed-off-by: Felipe Balbi --- drivers/irqchip/irq-omap-intc.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c index e97b535..7681b13 100644 --- a/drivers/irqchip/irq-omap-intc.c +++ b/drivers/irqchip/irq-omap-intc.c @@ -51,6 +51,8 @@ #define INTCPS_NR_ILR_REGS 128 #define INTCPS_NR_MIR_REGS 3 +#define INTC_PROTECTION_ENABLE (1 << 0) + /* * OMAP2 has a number of different interrupt controllers, each interrupt * controller is identified as its own "bank". Register definitions are @@ -290,12 +292,28 @@ static int __init omap_init_irq_legacy(u32 base) return 0; } +static void __init omap_irq_enable_protection(void) +{ + u32 reg; + + reg = intc_readl(INTC_PROTECTION); + reg |= INTC_PROTECTION_ENABLE; + intc_writel(INTC_PROTECTION, reg); +} + static int __init omap_init_irq(u32 base, struct device_node *node) { + int ret; + if (node) - return omap_init_irq_of(node); + ret = omap_init_irq_of(node); else - return omap_init_irq_legacy(base); + ret = omap_init_irq_legacy(base); + + if (ret == 0) + omap_irq_enable_protection(); + + return ret; } static asmlinkage void __exception_irq_entry