From patchwork Mon Sep 8 14:10:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 36993 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f199.google.com (mail-pd0-f199.google.com [209.85.192.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 70F9420DE9 for ; Mon, 8 Sep 2014 14:11:33 +0000 (UTC) Received: by mail-pd0-f199.google.com with SMTP id v10sf34481414pde.2 for ; Mon, 08 Sep 2014 07:11:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=FOCkKHfu+3olZ1qiYmSGewGH6iKCyf2oPuP0FUMVcM0=; b=AilBL4fBJRIlVtjyxhHZZXp2rKJkMotmW38nfPOy1r9zKoceTAyaGjQ5qIw8mafemd otHK/Y3Di9gcT4E6xKHw5EoN233WlgP2Qlpd5cZhylBbv0WBypFkwzunvxWXymyO3mio tteEGzREoSyI0/reqkVO6ZZHPn/m1VMvNSrgUlsdVF9hGrICqV8V2pe8xVKZCR8/Ud1k x2mdScK//f0jYBF+quFdX6DS+iPj/Nkw1NpbmoiWGaO75WZjuCs88t2LbFW9/KwHh04D gVZFa84Fdm5ZfDzyt7xaxItXuk0znOQ9AQftTzHb3lXqvB/sfeGa9t+qwKMN6M7xeNQz 44PA== X-Gm-Message-State: ALoCoQl9XKq3ECCyOGOwmcSLErBNCE3R4LYM5ScEOV30BjXZT92hdxDKgbl11r9Szzm7yNgeI89g X-Received: by 10.66.218.162 with SMTP id ph2mr17877485pac.3.1410185492772; Mon, 08 Sep 2014 07:11:32 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.104.130 with SMTP id a2ls1733864qgf.90.gmail; Mon, 08 Sep 2014 07:11:32 -0700 (PDT) X-Received: by 10.52.8.130 with SMTP id r2mr769355vda.53.1410185492607; Mon, 08 Sep 2014 07:11:32 -0700 (PDT) Received: from mail-vc0-f170.google.com (mail-vc0-f170.google.com [209.85.220.170]) by mx.google.com with ESMTPS id rl7si3928715vcb.85.2014.09.08.07.11.32 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 08 Sep 2014 07:11:32 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) client-ip=209.85.220.170; Received: by mail-vc0-f170.google.com with SMTP id hy4so837129vcb.1 for ; Mon, 08 Sep 2014 07:11:32 -0700 (PDT) X-Received: by 10.52.106.168 with SMTP id gv8mr190846vdb.80.1410185492384; Mon, 08 Sep 2014 07:11:32 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.45.67 with SMTP id uj3csp139980vcb; Mon, 8 Sep 2014 07:11:31 -0700 (PDT) X-Received: by 10.66.119.175 with SMTP id kv15mr21034944pab.30.1410185491472; Mon, 08 Sep 2014 07:11:31 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id uj6si18219842pab.63.2014.09.08.07.11.30 for ; Mon, 08 Sep 2014 07:11:31 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754503AbaIHOL3 (ORCPT + 5 others); Mon, 8 Sep 2014 10:11:29 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:58839 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753129AbaIHOL0 (ORCPT ); Mon, 8 Sep 2014 10:11:26 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s88EAww9017281; Mon, 8 Sep 2014 09:10:58 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s88EAw0c023752; Mon, 8 Sep 2014 09:10:58 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Mon, 8 Sep 2014 09:10:58 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s88EAi09014173; Mon, 8 Sep 2014 09:10:55 -0500 From: Roger Quadros To: , , CC: , , , , , , , , , Roger Quadros Subject: [PATCH 03/13] net: can: c_can: Add support for START pulse in RAMINIT sequence Date: Mon, 8 Sep 2014 17:10:32 +0300 Message-ID: <1410185442-907-4-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1410185442-907-1-git-send-email-rogerq@ti.com> References: <1410185442-907-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Some SoCs e.g. (TI DRA7xx) need a START pulse to start the RAMINIT sequence i.e. START bit must be set and cleared before checking for the DONE bit status. Add a new DT property "raminit-pulse" to specify if this mechanism must be used for RAMINIT. Signed-off-by: Roger Quadros --- Documentation/devicetree/bindings/net/can/c_can.txt | 3 +++ drivers/net/can/c_can/c_can.h | 1 + drivers/net/can/c_can/c_can_platform.c | 8 ++++++++ 3 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt index 0856209..2f0a6bb 100644 --- a/Documentation/devicetree/bindings/net/can/c_can.txt +++ b/Documentation/devicetree/bindings/net/can/c_can.txt @@ -19,6 +19,9 @@ Optional properties: register within the syscon region - raminit-start-bit : Bit posistion of START bit in the RAMINIT register - raminit-done-bit : Bit position of DONE bit in the RAMINIT register +- raminit-pulse : Property must exist if START pulse is needed for RAMINIT + sequence i.e. START bit will be set and cleared before + checking for DONE bit. Note: "ti,hwmods" field is used to fetch the base address and irq resources from TI, omap hwmod data base during device registration. diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h index bf68822..85b5ad0 100644 --- a/drivers/net/can/c_can/c_can.h +++ b/drivers/net/can/c_can/c_can.h @@ -175,6 +175,7 @@ struct c_can_raminit { unsigned int reg; /* register index within syscon */ u8 start_bit; /* START bit position in raminit reg. */ u8 done_bit; /* DONE bit position in raminit reg. */ + bool needs_pulse; /* If set, sets and clears START bit (pulse) */ }; /* c_can private data structure */ diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c index e7ec3b6..bc09695 100644 --- a/drivers/net/can/c_can/c_can_platform.c +++ b/drivers/net/can/c_can/c_can_platform.c @@ -123,6 +123,12 @@ static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable) ctrl |= 1 << raminit->start_bit; regmap_write(raminit->syscon, raminit->reg, ctrl); + /* clear START bit if start pulse is needed */ + if (raminit->needs_pulse) { + ctrl &= ~(1 << raminit->start_bit); + regmap_write(raminit->syscon, raminit->reg, ctrl); + } + ctrl |= 1 << raminit->done_bit; c_can_hw_raminit_wait_syscon(priv, mask, ctrl); } @@ -343,6 +349,8 @@ static int c_can_plat_probe(struct platform_device *pdev) } priv->raminit_sys.done_bit = val; + priv->raminit_sys.needs_pulse = of_property_read_bool(np, + "raminit-pulse"); priv->raminit = c_can_hw_raminit_syscon; break; default: