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[209.132.180.67]) by mx.google.com with ESMTP id xy3si2904560pbb.230.2014.07.17.09.46.01; Thu, 17 Jul 2014 09:46:01 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757418AbaGQQqA (ORCPT + 8 others); Thu, 17 Jul 2014 12:46:00 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:34619 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752443AbaGQQp7 (ORCPT ); Thu, 17 Jul 2014 12:45:59 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6HGjaok021859; Thu, 17 Jul 2014 11:45:36 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6HGjamw005710; Thu, 17 Jul 2014 11:45:36 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Thu, 17 Jul 2014 11:45:36 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6HGjaGl023861; Thu, 17 Jul 2014 11:45:36 -0500 Received: from localhost (j-172-22-151-213.vpn.ti.com [172.22.151.213]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s6HGjZt19605; Thu, 17 Jul 2014 11:45:35 -0500 (CDT) From: Dan Murphy To: , , CC: , Dan Murphy Subject: [v3 PATCH 5/6] ARM: dts: dra7: Add prm_resets node Date: Thu, 17 Jul 2014 11:45:30 -0500 Message-ID: <1405615531-15649-5-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405615531-15649-1-git-send-email-dmurphy@ti.com> References: <1405615531-15649-1-git-send-email-dmurphy@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: dmurphy@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add the prcm_resets node to the prm parent node. Add the draxx_resets file to define the dra7xx reset lines that are handled by this reset framework. Signed-off-by: Dan Murphy --- v3 - No changes arch/arm/boot/dts/dra7.dtsi | 7 +++ arch/arm/boot/dts/dra7xx-resets.dtsi | 82 ++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 arch/arm/boot/dts/dra7xx-resets.dtsi diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 8012763..f3a8819 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -93,6 +93,12 @@ prm_clockdomains: clockdomains { }; + + prm_resets: resets { + #address-cells = <1>; + #size-cells = <1>; + #reset-cells = <1>; + }; }; cm_core_aon: cm_core_aon@4a005000 { @@ -998,3 +1004,4 @@ }; /include/ "dra7xx-clocks.dtsi" +/include/ "dra7xx-resets.dtsi" diff --git a/arch/arm/boot/dts/dra7xx-resets.dtsi b/arch/arm/boot/dts/dra7xx-resets.dtsi new file mode 100644 index 0000000..4c4966d --- /dev/null +++ b/arch/arm/boot/dts/dra7xx-resets.dtsi @@ -0,0 +1,82 @@ +/* + * Device Tree Source for DRA7XX reset data + * + * Copyright (C) 2014 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&prm_resets { + dsp_rstctrl { + reg = <0x410>, + <0x414>; + + dsp_reset: dsp_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + + dsp_mmu_reset: dsp_mmu_reset { + control-bit = <0x02>; + status-bit = <0x02>; + }; + }; + + ipu_rstctrl { + reg = <0x510>, + <0x514>; + + ipu_cpu0_reset: ipu_cpu0_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + + ipu_cpu1_reset: ipu_cpu1_reset { + control-bit = <0x02>; + status-bit = <0x02>; + }; + + ipu_mmu_reset: ipu_mmu_reset { + control-bit = <0x04>; + status-bit = <0x04>; + }; + }; + + iva_rstctrl { + reg = <0xf10>, + <0xf14>; + + iva_reset: iva_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + + pcie_rstctrl { + reg = <0x1310>, + <0x1314>; + + pcie1_reset: pcie1_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + + pcie2_reset: pcie2_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + + device_rstctrl { + reg = <0x1D00>, + <0x1D04>; + + device_reset: device_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + +};