From patchwork Fri Jul 4 14:10:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 33100 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f72.google.com (mail-pa0-f72.google.com [209.85.220.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E9938203AC for ; Fri, 4 Jul 2014 14:10:51 +0000 (UTC) Received: by mail-pa0-f72.google.com with SMTP id rd3sf10325350pab.11 for ; Fri, 04 Jul 2014 07:10:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=CSBEzewyEQWO8Ak8M9x60g+32nmh2HnBwamxmScXli8=; b=NVoUOXAwp4jCkR/PvG1t23IHV6kmapGUduBgdlpIPslwWeiBKcBxThnNFT8GAhd+/f Ekd8AxqLWgGYWvOiU/hkBf69gRWqMD7bDIRFCOUt18YhlrU4TaMoFsTzf1V3kaMusrbO F1WhO2L4IsWSJxoGlrB49bkTK43uX2DigIxjOsCOLvk5xgbiw5B0Lt+AjZkZzwWWyrME YbWnDwIacqAmUZnlqHwI7xDd/nYGA5tWIyEgb7nlTaXh5ck3g+7th8uq2TQg1JHk9GSY nBr5DtaKThlrh76NkG29u8bpzVz1jCk9vTnQFMkZd19IDh3cr13uG+15odNHpQF9tFgB 9PGQ== X-Gm-Message-State: ALoCoQkhwOg7qgOcy9jD36/eK+vYFH2wDdpLyIkkp7TS4DWUZ7I5UtpqYFJAx+45q83+D9oM57Ir X-Received: by 10.66.147.197 with SMTP id tm5mr5608479pab.24.1404483051290; Fri, 04 Jul 2014 07:10:51 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.47.179 with SMTP id m48ls943790qga.84.gmail; Fri, 04 Jul 2014 07:10:51 -0700 (PDT) X-Received: by 10.52.121.112 with SMTP id lj16mr8333576vdb.29.1404483051119; Fri, 04 Jul 2014 07:10:51 -0700 (PDT) Received: from mail-vc0-f179.google.com (mail-vc0-f179.google.com [209.85.220.179]) by mx.google.com with ESMTPS id kf15si15530949vdb.100.2014.07.04.07.10.51 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 04 Jul 2014 07:10:51 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) client-ip=209.85.220.179; Received: by mail-vc0-f179.google.com with SMTP id id10so1657156vcb.10 for ; Fri, 04 Jul 2014 07:10:51 -0700 (PDT) X-Received: by 10.58.188.199 with SMTP id gc7mr9935997vec.4.1404483051044; Fri, 04 Jul 2014 07:10:51 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp468963vcb; Fri, 4 Jul 2014 07:10:50 -0700 (PDT) X-Received: by 10.68.139.225 with SMTP id rb1mr870264pbb.153.1404483047104; Fri, 04 Jul 2014 07:10:47 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ci1si2000775pdb.431.2014.07.04.07.10.46; Fri, 04 Jul 2014 07:10:46 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758722AbaGDOKp (ORCPT + 6 others); Fri, 4 Jul 2014 10:10:45 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:55087 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756085AbaGDOKn (ORCPT ); Fri, 4 Jul 2014 10:10:43 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s64EAMKI007433; Fri, 4 Jul 2014 09:10:22 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s64EALjO028480; Fri, 4 Jul 2014 09:10:21 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Fri, 4 Jul 2014 09:10:21 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s64EA8Em016874; Fri, 4 Jul 2014 09:10:20 -0500 From: Tero Kristo To: , , CC: Subject: [PATCH 06/10] ARM: OMAP24xx: PRM: add API for clearing wakeup status bits Date: Fri, 4 Jul 2014 17:10:31 +0300 Message-ID: <1404483035-21666-7-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1404483035-21666-1-git-send-email-t-kristo@ti.com> References: <1404483035-21666-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: t-kristo@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This helps to isolate the PRM into its own driver. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pm24xx.c | 31 +++++++++++++------------------ arch/arm/mach-omap2/prm2xxx.c | 18 ++++++++++++++++++ arch/arm/mach-omap2/prm2xxx.h | 1 + 3 files changed, 32 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a5ea988..d76694b 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void) /* Clear old wake-up events */ /* REVISIT: These write to reserved bits? */ - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); + omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); @@ -104,23 +104,18 @@ no_sleep: clk_enable(osc_ck); /* clear CORE wake-up events */ - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ - omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); + omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1); /* MPU domain wake events */ - l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); - if (l & 0x01) - omap2_prm_write_mod_reg(0x01, OCP_MOD, - OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); - if (l & 0x20) - omap2_prm_write_mod_reg(0x20, OCP_MOD, - OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, + 0x1); - /* Mask future PRCM-to-MPU interrupts */ - omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, + 0x20); pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); @@ -148,9 +143,9 @@ static void omap2_enter_mpu_retention(void) * it is in retention mode. */ if (omap2_allow_mpu_retention()) { /* REVISIT: These write to reserved bits? */ - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); + omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); /* Try to enter MPU retention */ pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c index a3a3cca..8695805 100644 --- a/arch/arm/mach-omap2/prm2xxx.c +++ b/arch/arm/mach-omap2/prm2xxx.c @@ -114,6 +114,24 @@ void omap2xxx_prm_dpll_reset(void) omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL); } +/** + * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module + * @module: PRM module to clear wakeups from + * @regs: register offset to clear + * @wkst_mask: wakeup status mask to clear + * + * Clears wakeup status bits for a given module, so that the device can + * re-enter idle. + */ +void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask) +{ + u32 wkst; + + wkst = omap2_prm_read_mod_reg(module, regs); + wkst &= wkst_mask; + omap2_prm_write_mod_reg(wkst, module, regs); +} + int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) { omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h index d2cb636..d734141 100644 --- a/arch/arm/mach-omap2/prm2xxx.h +++ b/arch/arm/mach-omap2/prm2xxx.h @@ -125,6 +125,7 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); extern void omap2xxx_prm_dpll_reset(void); +void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); extern int __init omap2xxx_prm_init(void);