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[209.132.180.67]) by mx.google.com with ESMTP id cl5si29620598pad.108.2014.07.02.01.48.10; Wed, 02 Jul 2014 01:48:10 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752005AbaGBIsH (ORCPT + 6 others); Wed, 2 Jul 2014 04:48:07 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:38803 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751897AbaGBIsC (ORCPT ); Wed, 2 Jul 2014 04:48:02 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s628lgqk013420; Wed, 2 Jul 2014 03:47:42 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s628lgMR013341; Wed, 2 Jul 2014 03:47:42 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Wed, 2 Jul 2014 03:47:42 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s628lOXe007645; Wed, 2 Jul 2014 03:47:41 -0500 From: Tero Kristo To: , , , CC: Subject: [PATCH 08/13] ARM: OMAP2+: clock/dpll: convert bypass check to use clk_features Date: Wed, 2 Jul 2014 11:47:42 +0300 Message-ID: <1404290867-6768-9-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1404290867-6768-1-git-send-email-t-kristo@ti.com> References: <1404290867-6768-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: t-kristo@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses clk_features data provided during boot. This avoids the need to use cpu_is_X type checks runtime, and allows us to eventually move the clock code under the clock driver. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clkt_dpll.c | 25 +++++++++++++------------ arch/arm/mach-omap2/clock.c | 17 +++++++++++++++++ arch/arm/mach-omap2/clock.h | 1 + 3 files changed, 31 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index f1b052a..51f995a 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -184,18 +184,19 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, */ static int _omap2_dpll_is_in_bypass(u32 v) { - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) + u8 mask, val; + + mask = ti_clk_features.dpll_bypass_vals; + + /* + * Each set bit in the mask corresponds to a bypass value equal + * to the bitshift. Go through each set-bit in the mask and + * compare against the given register value. + */ + while (mask) { + val = __ffs(mask); + mask ^= (1 << val); + if (v == val) return 1; } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7efe66e..e438437 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -767,4 +767,21 @@ void __init ti_clk_init_features(void) ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; } + + /* Bypass value setup for DPLLs */ + if (cpu_is_omap24xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP2XXX_EN_DPLL_FRBYPASS); + } else if (cpu_is_omap34xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP3XXX_EN_DPLL_FRBYPASS); + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || + soc_is_omap54xx() || soc_is_dra7xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | + (1 << OMAP4XXX_EN_DPLL_MNBYPASS); + } } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 02aa2e3..7b2b099 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -232,6 +232,7 @@ struct ti_clk_features { long fint_max; long fint_band1_max; long fint_band2_min; + u8 dpll_bypass_vals; }; extern struct ti_clk_features ti_clk_features;