From patchwork Wed Jul 2 08:47:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 32945 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qc0-f200.google.com (mail-qc0-f200.google.com [209.85.216.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 6E03820560 for ; Wed, 2 Jul 2014 08:48:02 +0000 (UTC) Received: by mail-qc0-f200.google.com with SMTP id o8sf25433794qcw.7 for ; Wed, 02 Jul 2014 01:48:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=/YdcXbp2/ONAB9yKrKof8F4wO4uQ9AonQQPgyz79zmA=; b=i0xZ5HSlgybX6ykGK+et0TIXUkdGh75EG0oXq3qaPy3BXjf6WWex7jYYFkWdH1okZ+ mBRbL4Vcp7Ol/XEfHMg1kL22foPWa4MkBUPnAuI/tSABO4x/JUlPZXzz/Ck1hkdVk/LO xH2Bolp86HNzgBwBOr6U5A9al6k2mSU2yPilOdi6vwbnWex6Mwnzx+h9ToZ9X8umk5TI siWjQ2tFB+xR84qhOYp8obd/OSykHJwzmulUav4Wjl77iDJ7sBL7cCDuwB/5zCunH/vt F7zQIVoxcWD17DDIbWZfpLdx0jBcuxA9PFlFsNu7VkP36sGYPfdqPbFqGn89uPkuj6TJ aQzQ== X-Gm-Message-State: ALoCoQn4TjwDNTYFTRWpRkU2iYPBXnqb7BFrA7ewWdtt0XuOj2KaBfzwcFzMvRH5ntHgscxyY0ah X-Received: by 10.236.229.161 with SMTP id h31mr5659799yhq.21.1404290882286; Wed, 02 Jul 2014 01:48:02 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.51.3 with SMTP id t3ls2228733qga.82.gmail; Wed, 02 Jul 2014 01:48:02 -0700 (PDT) X-Received: by 10.220.161.8 with SMTP id p8mr48390344vcx.4.1404290882205; Wed, 02 Jul 2014 01:48:02 -0700 (PDT) Received: from mail-vc0-f170.google.com (mail-vc0-f170.google.com [209.85.220.170]) by mx.google.com with ESMTPS id ur5si12630116vec.61.2014.07.02.01.48.02 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 02 Jul 2014 01:48:02 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) client-ip=209.85.220.170; Received: by mail-vc0-f170.google.com with SMTP id hy10so10062734vcb.15 for ; Wed, 02 Jul 2014 01:48:02 -0700 (PDT) X-Received: by 10.52.163.208 with SMTP id yk16mr4955142vdb.36.1404290882104; Wed, 02 Jul 2014 01:48:02 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp277208vcb; Wed, 2 Jul 2014 01:48:01 -0700 (PDT) X-Received: by 10.66.119.136 with SMTP id ku8mr2457395pab.121.1404290881323; Wed, 02 Jul 2014 01:48:01 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id cl5si29620598pad.108.2014.07.02.01.48.00; Wed, 02 Jul 2014 01:48:00 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752001AbaGBIr7 (ORCPT + 6 others); Wed, 2 Jul 2014 04:47:59 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:54384 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751525AbaGBIr6 (ORCPT ); Wed, 2 Jul 2014 04:47:58 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s628lcWM031776; Wed, 2 Jul 2014 03:47:38 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s628lcB9013324; Wed, 2 Jul 2014 03:47:38 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Wed, 2 Jul 2014 03:47:38 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s628lOXc007645; Wed, 2 Jul 2014 03:47:37 -0500 From: Tero Kristo To: , , , CC: Subject: [PATCH 06/13] ARM: OMAP2+: clock: add fint values to the ti_clk_features struct Date: Wed, 2 Jul 2014 11:47:40 +0300 Message-ID: <1404290867-6768-7-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1404290867-6768-1-git-send-email-t-kristo@ti.com> References: <1404290867-6768-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: t-kristo@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , These are SoC specific and get their init values based on the SoC type. Previously the values were hard coded within the DPLL clock code, but having them inside the clock features avoids runtime cpu_is_X type checks. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clkt_dpll.c | 34 ++++++++++++---------------------- arch/arm/mach-omap2/clock.c | 23 +++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 4 ++++ 3 files changed, 39 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 5aa734a..5207e84 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -44,20 +44,12 @@ #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) -/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ -#define OMAP3430_DPLL_FINT_BAND1_MIN 750000 -#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 -#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 -#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 - /* * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. * From device data manual section 4.3 "DPLL and DLL Specifications". */ #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 -#define OMAP3PLUS_DPLL_FINT_MIN 32000 -#define OMAP3PLUS_DPLL_FINT_MAX 52000000 /* _dpll_test_fint() return codes */ #define DPLL_FINT_UNDERFLOW -1 @@ -87,33 +79,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, int n) /* DPLL divider must result in a valid jitter correction val */ fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; - if (cpu_is_omap24xx()) { - /* Should not be called for OMAP2, so warn if it is called */ - WARN(1, "No fint limits available for OMAP2!\n"); - return DPLL_FINT_INVALID; - } else if (cpu_is_omap3430()) { - fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; - fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; - } else if (dd->flags & DPLL_J_TYPE) { + if (dd->flags & DPLL_J_TYPE) { fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; } else { - fint_min = OMAP3PLUS_DPLL_FINT_MIN; - fint_max = OMAP3PLUS_DPLL_FINT_MAX; + fint_min = ti_clk_features.fint_min; + fint_max = ti_clk_features.fint_max; + } + + if (!fint_min || !fint_max) { + WARN(1, "No fint limits available!\n"); + return DPLL_FINT_INVALID; } - if (fint < fint_min) { + if (fint < ti_clk_features.fint_min) { pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", n); dd->max_divider = n; ret = DPLL_FINT_UNDERFLOW; - } else if (fint > fint_max) { + } else if (fint > ti_clk_features.fint_max) { pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", n); dd->min_divider = n; ret = DPLL_FINT_INVALID; - } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX && - fint < OMAP3430_DPLL_FINT_BAND2_MIN) { + } else if (fint > ti_clk_features.fint_band1_max && + fint < ti_clk_features.fint_band2_min) { pr_debug("rejecting n=%d due to Fint failure\n", n); ret = DPLL_FINT_INVALID; } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7897053..7efe66e 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -51,6 +51,19 @@ u16 cpu_mask; */ struct ti_clk_features ti_clk_features; +/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ +#define OMAP3430_DPLL_FINT_BAND1_MIN 750000 +#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 +#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 +#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 + +/* + * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. + * From device data manual section 4.3 "DPLL and DLL Specifications". + */ +#define OMAP3PLUS_DPLL_FINT_MIN 32000 +#define OMAP3PLUS_DPLL_FINT_MAX 52000000 + /* * clkdm_control: if true, then when a clock is enabled in the * hardware, its clockdomain will first be enabled; and when a clock @@ -744,4 +757,14 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, */ void __init ti_clk_init_features(void) { + /* Fint setup for DPLLs */ + if (cpu_is_omap3430()) { + ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; + ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; + ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; + ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; + } else { + ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; + ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; + } } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 9b89cc0..02aa2e3 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -228,6 +228,10 @@ extern u16 cpu_mask; */ struct ti_clk_features { u32 flags; + long fint_min; + long fint_max; + long fint_band1_max; + long fint_band2_min; }; extern struct ti_clk_features ti_clk_features;