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[209.132.180.67]) by mx.google.com with ESMTP id cl5si29620598pad.108.2014.07.02.01.48.12; Wed, 02 Jul 2014 01:48:12 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752037AbaGBIsK (ORCPT + 6 others); Wed, 2 Jul 2014 04:48:10 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:39733 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751825AbaGBIsH (ORCPT ); Wed, 2 Jul 2014 04:48:07 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s628ligj026451; Wed, 2 Jul 2014 03:47:44 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s628liom013346; Wed, 2 Jul 2014 03:47:44 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 2 Jul 2014 03:47:44 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s628lOXf007645; Wed, 2 Jul 2014 03:47:43 -0500 From: Tero Kristo To: , , , CC: Subject: [PATCH 09/13] ARM: OMAP2+: clock/dpll: add jitter correction behind clk_features Date: Wed, 2 Jul 2014 11:47:43 +0300 Message-ID: <1404290867-6768-10-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1404290867-6768-1-git-send-email-t-kristo@ti.com> References: <1404290867-6768-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: t-kristo@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.177 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Currently DPLL code uses runtime cpu_is_343x checks to see if the DPLL has freqsel fields in its control register or not. Instead, add a new flag to the clk_features.flags and use this during runtime. Allows eventual move of the DPLL code under clock driver. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 4 ++++ arch/arm/mach-omap2/clock.h | 3 +++ arch/arm/mach-omap2/dpll3xxx.c | 4 ++-- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e438437..23b5f05 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -784,4 +784,8 @@ void __init ti_clk_init_features(void) (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | (1 << OMAP4XXX_EN_DPLL_MNBYPASS); } + + /* Jitter correction only available on OMAP343X */ + if (cpu_is_omap343x()) + ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 7b2b099..d3ef147 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -234,6 +234,9 @@ struct ti_clk_features { long fint_band2_min; u8 dpll_bypass_vals; }; + +#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0) + extern struct ti_clk_features ti_clk_features; extern const struct clkops clkops_omap2_dflt_wait; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 6d7ba37..12ad0f5 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -310,7 +310,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) * Set jitter correction. Jitter correction applicable for OMAP343X * only since freqsel field is no longer present on other devices. */ - if (cpu_is_omap343x()) { + if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { v = omap2_clk_readl(clk, dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -512,7 +512,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; /* Freqsel is available only on OMAP343X devices */ - if (cpu_is_omap343x()) { + if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); WARN_ON(!freqsel);