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[209.132.180.67]) by mx.google.com with ESMTP id hq3si28727976pad.87.2014.05.21.04.22.24; Wed, 21 May 2014 04:22:24 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752475AbaEULWH (ORCPT + 27 others); Wed, 21 May 2014 07:22:07 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:36796 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752395AbaEULWE (ORCPT ); Wed, 21 May 2014 07:22:04 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s4LBLfEj014583; Wed, 21 May 2014 06:21:41 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4LBLfgt021143; Wed, 21 May 2014 06:21:41 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Wed, 21 May 2014 06:21:40 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4LBLAAc018495; Wed, 21 May 2014 06:21:37 -0500 From: Roger Quadros To: , CC: , , , , , , , , , , , Roger Quadros Subject: [RFC PATCH 07/16] ARM: OMAP2+: nand: Update gpmc_nand_init() to use generic_gpmc_init() Date: Wed, 21 May 2014 14:20:55 +0300 Message-ID: <1400671264-10702-8-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400671264-10702-1-git-send-email-rogerq@ti.com> References: <1400671264-10702-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This function should only be called by board init code for legacy boot. Signed-off-by: Roger Quadros --- arch/arm/mach-omap2/gpmc-nand.c | 79 ++++++++--------------------------------- 1 file changed, 14 insertions(+), 65 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 4349e82..d536575 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -25,8 +25,11 @@ #define NAND_IO_SIZE 4 static struct resource gpmc_nand_resource[] = { +/* GPMC driver will fixup all the resources, see gpmc_probe_legacy () */ { .flags = IORESOURCE_MEM, + .start = 0, + .end = NAND_IO_SIZE - 1, }, { .flags = IORESOURCE_IRQ, @@ -72,89 +75,35 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) return 0; } -/* This function will go away once the device-tree convertion is complete */ -static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data, - struct gpmc_settings *s) -{ - /* Enable RD PIN Monitoring Reg */ - if (gpmc_nand_data->dev_ready) { - s->wait_on_read = true; - s->wait_on_write = true; - } - - if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) - s->device_width = GPMC_DEVWIDTH_16BIT; - else - s->device_width = GPMC_DEVWIDTH_8BIT; -} - int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, struct gpmc_timings *gpmc_t) { int err = 0; struct gpmc_settings s; - struct device *dev = &gpmc_nand_device.dev; memset(&s, 0, sizeof(struct gpmc_settings)); - gpmc_nand_device.dev.platform_data = gpmc_nand_data; - err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, - (unsigned long *)&gpmc_nand_resource[0].start); - if (err < 0) { - dev_err(dev, "Cannot request GPMC CS %d, error %d\n", - gpmc_nand_data->cs, err); - return err; - } - - gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + - NAND_IO_SIZE - 1; - - gpmc_nand_resource[1].start = - gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); - gpmc_nand_resource[2].start = - gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); - - if (gpmc_t) { - err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); - if (err < 0) { - dev_err(dev, "Unable to set gpmc timings: %d\n", err); - return err; - } - } - - if (gpmc_nand_data->of_node) - gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); + /* GPMC settings */ + if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) + s.device_width = GPMC_DEVWIDTH_16BIT; else - gpmc_set_legacy(gpmc_nand_data, &s); + s.device_width = GPMC_DEVWIDTH_8BIT; s.device_nand = true; - err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); - if (err < 0) - goto out_free_cs; - - err = gpmc_configure(GPMC_CONFIG_WP, 0); - if (err < 0) - goto out_free_cs; - - gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); - if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { - dev_err(dev, "Unsupported NAND ECC scheme selected\n"); + pr_err("%s: Unsupported NAND ECC scheme selected\n", __func__); return -EINVAL; } - err = platform_device_register(&gpmc_nand_device); - if (err < 0) { - dev_err(dev, "Unable to register NAND device\n"); - goto out_free_cs; + err = gpmc_generic_init(gpmc_nand_data->cs, GPMC_OMAP_TYPE_NAND, &s, + NULL, gpmc_t, &gpmc_nand_device, + sizeof(*gpmc_nand_data)); + if (err) { + pr_err("%s: gpmc_generic_init() failed %d\n", __func__, err); + return err; } return 0; - -out_free_cs: - gpmc_cs_free(gpmc_nand_data->cs); - - return err; }