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[209.132.180.67]) by mx.google.com with ESMTP id ka6si1019226pbc.310.2014.04.23.10.36.03; Wed, 23 Apr 2014 10:36:03 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757397AbaDWRfu (ORCPT + 27 others); Wed, 23 Apr 2014 13:35:50 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:58092 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932395AbaDWRfr (ORCPT ); Wed, 23 Apr 2014 13:35:47 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3NHZhVi023076; Wed, 23 Apr 2014 12:35:43 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3NHZhNM024585; Wed, 23 Apr 2014 12:35:43 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Wed, 23 Apr 2014 12:35:43 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3NHZdSw006189; Wed, 23 Apr 2014 12:35:40 -0500 From: Roger Quadros To: CC: , , , , , , , , Benoit Cousson , Roger Quadros Subject: [PATCH v4 2/4] ARM: dts: omap5: add sata node Date: Wed, 23 Apr 2014 20:35:33 +0300 Message-ID: <1398274533-24735-1-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1398274237-24510-1-git-send-email-rogerq@ti.com> References: <1398274237-24510-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Balaji T K Add support for sata. [Roger Q] Clean up. CC: Benoit Cousson CC: Tony Lindgren Signed-off-by: Balaji T K Signed-off-by: Roger Quadros --- arch/arm/boot/dts/omap5.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 6f3de22..8ab6721 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -863,6 +863,46 @@ #thermal-sensor-cells = <1>; }; + + omap_control_sata: control-phy@4a002374 { + compatible = "ti,control-phy-pipe3"; + reg = <0x4a002374 0x4>; + reg-names = "power"; + clocks = <&sys_clkin>; + clock-names = "sysclk"; + }; + + /* OCP2SCP3 */ + ocp2scp@4a090000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x4a090000 0x20>; + ranges; + ti,hwmods = "ocp2scp3"; + sata_phy: phy@4a096000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x4A096000 0x80>, /* phy_rx */ + <0x4A096400 0x64>, /* phy_tx */ + <0x4A096800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + ctrl-module = <&omap_control_sata>; + clocks = <&sys_clkin>; + clock-names = "sysclk"; + #phy-cells = <0>; + }; + }; + + sata: sata@4a141100 { + compatible = "snps,dwc-ahci"; + reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; + interrupts = ; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&sata_ref_clk>; + ti,hwmods = "sata"; + }; + }; };