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[209.132.180.67]) by mx.google.com with ESMTP id eb3si4028506pbc.116.2014.01.09.06.03.11; Thu, 09 Jan 2014 06:03:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755982AbaAIODH (ORCPT + 5 others); Thu, 9 Jan 2014 09:03:07 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:46915 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755850AbaAIOCv (ORCPT ); Thu, 9 Jan 2014 09:02:51 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s09E2LuV021149; Thu, 9 Jan 2014 08:02:21 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s09E2L4O025249; Thu, 9 Jan 2014 08:02:21 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Thu, 9 Jan 2014 08:02:20 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s09E12WR030058; Thu, 9 Jan 2014 08:02:18 -0600 From: Tero Kristo To: , , , , , , CC: , , J Keerthy Subject: [PATCHv13 23/40] ARM: dts: clk: Add apll related clocks Date: Thu, 9 Jan 2014 16:00:34 +0200 Message-ID: <1389276051-1326-24-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1389276051-1326-1-git-send-email-t-kristo@ti.com> References: <1389276051-1326-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: t-kristo@ti.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.53 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: J Keerthy The patch adds a mux node to choose the parent of apll_pcie_ck node. Signed-off-by: J Keerthy Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 32df847..d4e7410 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1150,11 +1150,19 @@ ti,invert-autoidle-bit; }; + apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { + compatible = "ti,mux-clock"; + clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; + #clock-cells = <0>; + reg = <0x021c 0x4>; + ti,bit-shift = <7>; + }; + apll_pcie_ck: apll_pcie_ck { #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; + compatible = "ti,dra7-apll-clock"; + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; + reg = <0x021c>, <0x0220>; }; apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {