From patchwork Thu May 3 02:11:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omar Ramirez Luna X-Patchwork-Id: 8368 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C1AEE23E13 for ; Thu, 3 May 2012 02:12:08 +0000 (UTC) Received: from mail-gy0-f180.google.com (mail-gy0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7B61AA189EC for ; Thu, 3 May 2012 02:12:08 +0000 (UTC) Received: by ghbz12 with SMTP id z12so1737364ghb.11 for ; Wed, 02 May 2012 19:12:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=l/j4Gb8ok1V8+FMuzDpT65Ju8Dn0d4gnVeNAGLwdGRY=; b=cKcZZUQey7rw30d4l6Qt3Dfca0rmdzh/7E84ndRSa9QkT97kgyzbe3qqGVfAhrnFbx /+U+Ba1UMXOmJ/I6Gu+D7Nxi4/nHm/+HXMpuXbKlzcUAfuDqqvWh/LTKHx89Po+qu6Pu Zc0IP5eGSIMR56FS2Dp8gu3UracP5GOdWGchSUfouFeuDGzoi5iFmMjmGnvNUDO7q814 bg9Ks1UyF3jUSXNgCxqqN/Imu9QE7MdCLPteu2zSOPQheI/kzAKSNxkVnAwwP/DbJKTI ms2g/giJNKjIu0THR+sVqO8vIVsQJqo81qamtWjmHADoN3hU97IQ/ihj/0PFNWIp5M// ejjg== Received: by 10.50.41.196 with SMTP id h4mr213854igl.33.1336011127651; Wed, 02 May 2012 19:12:07 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp294431ibt; Wed, 2 May 2012 19:12:07 -0700 (PDT) Received: by 10.182.113.9 with SMTP id iu9mr606777obb.28.1336011126851; Wed, 02 May 2012 19:12:06 -0700 (PDT) Received: from mail-ob0-f178.google.com (mail-ob0-f178.google.com [209.85.214.178]) by mx.google.com with ESMTPS id k10si2270557oeb.22.2012.05.02.19.12.06 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 19:12:06 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of omar.luna@linaro.org) client-ip=209.85.214.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of omar.luna@linaro.org) smtp.mail=omar.luna@linaro.org Received: by mail-ob0-f178.google.com with SMTP id eq6so2407530obc.37 for ; Wed, 02 May 2012 19:12:06 -0700 (PDT) Received: by 10.182.159.41 with SMTP id wz9mr377430obb.69.1336011126638; Wed, 02 May 2012 19:12:06 -0700 (PDT) Received: from localhost.localdomain (dragon.ti.com. [192.94.94.33]) by mx.google.com with ESMTPS id r8sm3389007oer.6.2012.05.02.19.12.05 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 19:12:06 -0700 (PDT) From: Omar Ramirez Luna To: Tony Lindgren , Paul Walmsley , Kevin Hilman Cc: Russell King , Omar Ramirez Luna , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-dev@lists.linaro.org, Omar Ramirez Luna Subject: [PATCH 1/3] OMAP2+: control: new APIs to configure boot address and mode Date: Wed, 2 May 2012 21:11:51 -0500 Message-Id: <1336011113-31502-2-git-send-email-omar.luna@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1336011113-31502-1-git-send-email-omar.luna@linaro.org> References: <1336011113-31502-1-git-send-email-omar.luna@linaro.org> X-Gm-Message-State: ALoCoQmRbjevINgf4lVUw9fT9pUXOHvzugCTbJ6PqX2aELeUeX6VYCD2k6LRmDck2r4TQtbLvMls SCM contains boot addr and boot mode registers to control other processors on different OMAP versions. It controls the boot address and mode for DSP based subsystems like: IVA 2.1 (OMAP2430), IVA 2.2 (OMAP3) and DSP (OMAP4). If contained within SCM registers, when a processor is booting it uses BOOTADDR to start running the code at that location. BOOTMOD register specifies a different set of modes for the processor to execute when booting (from direct, idle, self-loop, user and default). Since there was no offset associated with OMAP4, this patch defines it. Signed-off-by: Omar Ramirez Luna --- arch/arm/mach-omap2/control.c | 43 ++++++++++++++++++++ arch/arm/mach-omap2/control.h | 2 + .../include/mach/ctrl_module_core_44xx.h | 1 + 3 files changed, 46 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 08e674b..3223b81 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -241,6 +241,49 @@ void omap3_ctrl_write_boot_mode(u8 bootmode) #endif +/** + * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor + * @bootaddr: physical address of the boot loader + * + * Set boot address for the boot loader of a supported processor + * when a power ON sequence occurs. + */ +void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) +{ + u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : + cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : + cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : + 0; + + if (!offset) { + pr_err("%s: unsupported omap type\n", __func__); + return; + } + + omap_ctrl_writel(bootaddr, offset); +} + +/** + * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor + * @bootmode: 8-bit value to pass to some boot code + * + * Sets boot mode for the boot loader of a supported processor + * when a power ON sequence occurs. + */ +void omap_ctrl_write_dsp_boot_mode(u8 bootmode) +{ + u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : + cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : + 0; + + if (!offset) { + pr_err("%s: unsupported omap type\n", __func__); + return; + } + + omap_ctrl_writel(bootmode, offset); +} + #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) /* * Clears the scratchpad contents in case of cold boot- diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index a406fd0..fcc98f8 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -397,6 +397,8 @@ extern u32 omap3_arm_context[128]; extern void omap3_control_save_context(void); extern void omap3_control_restore_context(void); extern void omap3_ctrl_write_boot_mode(u8 bootmode); +extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); +extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); #else diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h index 2f7ac70..0197082 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h @@ -42,6 +42,7 @@ #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 #define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 +#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320