From patchwork Fri Jan 3 22:54:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shree Ramamoorthy X-Patchwork-Id: 855116 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E359D1C4A0D; Fri, 3 Jan 2025 22:54:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735944871; cv=none; b=B7XjADuYXkAi58uT+4Yfd6N11sEK5kd5pV4DDfkbKh64A3znUBGRt03J4jtzl6YTDhPTNjx3bJkt48MglncGe1R0g2l5GskW3lCQQcyGWrPQs+xRPh/4iKp6kNBbUfvkWatU2bW9q3L2jA+g2QJFF9jnP1PDCLbAnSLLUcjTG7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735944871; c=relaxed/simple; bh=8osPZ56tY1QYMyiVPX+VHcslzNqRX6jzMKugViCk8ok=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=kFbc8EiFJyisVDKO1mrPgptYfei565VgcOV1hhVw/L04Zz9MDbxNuK4/XLDJwXnAjHQLK7aZbjT0LSIehwiFqbWSZkXNCKlIeZpVnIbO2YiSfpwvUY7sJ8rwJKnWNyay9AzLO8cEYyRD6FsuZFcd+dSgu+gBiK0Gl4QRpaZGdOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=k/jS7KZS; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="k/jS7KZS" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 503Ms7nl2150869 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 3 Jan 2025 16:54:07 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1735944847; bh=hZM5ViXAIdWtWtzfsy+KX+Pjyd2PTvM4pi378WAW72U=; h=From:To:CC:Subject:Date; b=k/jS7KZSK3FL8VX61N9jbvG6hn8oCFKLnrAaxM8QlJ2ZrQNkIm3IUcwhQeGt/KUXk iAruUuN9S/Wb0Z0tm8YkqgabaW39LE37kwEu6CKJKlpuZy/NvmcUUxFjahVTC+NUjL qBBVJaKSXJTQ0I5nVeQZWIosRWl2Xxp/ojbXYsh4= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 503Ms7RQ061295; Fri, 3 Jan 2025 16:54:07 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 3 Jan 2025 16:54:07 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 3 Jan 2025 16:54:07 -0600 Received: from DMZ007XYY.dhcp.ti.com (dmz007xyy.dhcp.ti.com [128.247.29.228]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 503Ms7AL098981; Fri, 3 Jan 2025 16:54:07 -0600 From: Shree Ramamoorthy To: , , , , , , , , , CC: , , Subject: [PATCH v2 0/3] Add TI TPS65215 PMIC GPIO Support Date: Fri, 3 Jan 2025 16:54:04 -0600 Message-ID: <20250103225407.196068-1-s-ramamoorthy@ti.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea TPS65215 is a Power Management Integrated Circuit (PMIC) that has significant register map overlap with TPS65219. The series introduces TPS65215 and restructures the existing driver to support multiple devices. This follow-up series is dependent on: Commit 25c86c81b0ad ("regulator: dt-bindings: Add TI TPS65215 PMIC bindings") Commit c3cc37e8d23d ("mfd: tps65215: Add support for TI TPS65215 PMIC") Commit 5f0f36835b90 ("mfd: tps65215: Remove regmap_read check") TPS65219 Cleanup Series: GPIO: https://lore.kernel.org/all/20241217204755.1011731-1-s-ramamoorthy@ti.com/ MFD: https://lore.kernel.org/all/20241217204935.1012106-1-s-ramamoorthy@ti.com/ Reg: https://lore.kernel.org/all/20241217204526.1010989-1-s-ramamoorthy@ti.com/ - Both TPS65215 and TPS65219 have 3 Buck regulators. - TPS65215 has 2 LDOs, whereas TPS65219 has 4 LDOs. - TPS65215 and TPS65219's LDO1 are the same. - TPS65215's LDO2 maps to TPS65219's LDO3. - TPS65215 has 1 GPO, whereas TPS65219 has 2 GPOs. - The remaining features are the same. TPS65215 TRM: https://www.ti.com/lit/pdf/slvucw5/ AM62L + TPS65215 Test Logs: https://gist.github.com/ramamoorthyhs/7560eca6110fafc77b51894fa2c0fd22 --- Change Log: v1 -> v2: - have any PMIC lists be in alpha-numeric order: TPS65215, then TPS65219 - remove comma after terminator - Add driver prefix to chip_data struct --- Shree Ramamoorthy (3): gpio: tps65215: Add TPS65215 to platform_device_id table gpio: tps65215: Update GPIO0_IDX macro prefix gpio tps65215: Add support for varying gpio/offset values drivers/gpio/gpio-tps65219.c | 54 +++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 13 deletions(-)