| Message ID | 20231108-fix-mips-nand-v1-0-5fc5586d04de@linaro.org |
|---|---|
| Headers | show |
| Series | Fix polarity and bindings for GPIO-based NAND drivers | expand |
Hi Linus, linus.walleij@linaro.org wrote on Wed, 08 Nov 2023 15:33:53 +0100: > The standard property for describing the band width of a NAND > memory is "nand-bus-width" not "bank-width". The new bindings > support both so make Linux check both in priority order. > > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > drivers/mtd/nand/raw/gpio.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/gpio.c b/drivers/mtd/nand/raw/gpio.c > index 5553101c709c..d5bd245b0c0d 100644 > --- a/drivers/mtd/nand/raw/gpio.c > +++ b/drivers/mtd/nand/raw/gpio.c > @@ -183,7 +183,15 @@ static int gpio_nand_get_config(struct device *dev, > { > u32 val; > > - if (!device_property_read_u32(dev, "bank-width", &val)) { > + /* The preferred binding takes precedence */ > + if (!device_property_read_u32(dev, "nand-bus-width", &val)) { > + if (val == 16) { > + chip->options |= NAND_BUSWIDTH_16; > + } else if (val != 8) { > + dev_err(dev, "invalid nand-bus-width %u\n", val); > + return -EINVAL; > + } > + } else if (!device_property_read_u32(dev, "bank-width", &val)) { > if (val == 2) { > chip->options |= NAND_BUSWIDTH_16; > } else if (val != 1) { > I'm not sure this is actually needed. I believe of_get_nand_bus_width is already called (nand_scan_ident -> rawnand_dt_init) and will set the NAND_BUSWIDTH_16 flag automatically. So the above 'if' is already a fallback. Maybe you can add a comment if you want to make this more explicit that the real property is nand-bus-width and the property parsed in the driver is for backward compatibility only? Thanks, Miquèl
The AMD Delta and generic GPIO-based NAND drivers are using GPIO lines extensively to communicate with a raw NAND flash. Some confusion has crept into the naming leading to the two drivers using inversed semantics differently for pins with the same name. Fix the situation by naming the pins consistently without any inversion names (such as nce for a negative active chip enable). Fix up all in-tree users. Next rewrite the device tree bindings in YAML schema, and fix up the single in-tree DTS file (MIPS) to use the new bindings where each signal is specified explicitly instead of an array with some "blanks" for unused lines. Last clean up the GPIO NAND driver to drop use of board file provided data as no boards using this remain, and use device properties removing the explicit reliance on device tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- Linus Walleij (6): mtd: rawnand: ams-delta/gpio: Unify polarity dt-bindings: mtd: Rewrite gpio-control-nand in schema MIPS: NI 169445: Fix NAND GPIOs mtd: rawnand: gpio: Use device properties mtd: rawnand: gpio: Support standard nand width mtd: rawnand: gpio: Rename file .../devicetree/bindings/mtd/gpio-control-nand.txt | 47 ------ .../devicetree/bindings/mtd/gpio-control-nand.yaml | 168 +++++++++++++++++++++ Documentation/devicetree/bindings/mtd/mtd.yaml | 2 +- arch/arm/mach-omap1/board-ams-delta.c | 8 +- arch/mips/boot/dts/ni/169445.dts | 13 +- drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/ams-delta.c | 60 ++++---- drivers/mtd/nand/raw/{gpio.c => nand-gpio.c} | 120 +++++---------- 8 files changed, 251 insertions(+), 169 deletions(-) --- base-commit: be3ca57cfb777ad820c6659d52e60bbdd36bf5ff change-id: 20231105-fix-mips-nand-c91ebd80fa4f Best regards,