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Niedermayr" To: , CC: , , , Subject: [PATCH v9 0/2] gpmc wait pin additions Date: Wed, 2 Nov 2022 14:30:45 +0100 Message-ID: <20221102133047.1654449-1-benedikt.niedermayr@siemens.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [139.21.146.184] X-ClientProxiedBy: DEMCHDC8WBA.ad011.siemens.net (139.25.226.105) To DEMCHDC8WAA.ad011.siemens.net (139.25.226.104) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB5EUR01FT054:EE_|AS8PR10MB7328:EE_ X-MS-Office365-Filtering-Correlation-Id: 36e21dbf-039d-41ee-4a3f-08dabcd67c32 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IpKJEhOKfQGgTB2jXJYo1tJx0fl7AkCJk2N0eBn4bTZM40rERtn4Ocgb02kqymAcU/PHSOeRw5fKtmrrjQ9M8xX8GuZqA32d9DlrY5Aby0Lkfqmv+64RZk0+/dSl40m2Qm0HRHRxLeiOJEUKPAPWBPDTQ0t6XJmy+gkcbQ+YAComFiEHZISFM6XA4GnrDENFJ83YutLG4p+CYPpeflr2C4peNb8+Vhi5My80w2RM4OYlcEh+U6L722VZEUykjwlCOU/aMtzKIkUaeBLDHubEfj7EGouDJ2J+n6nWM+Kj6UMmXXy4j+inGT0rpm97PypzBrRPvLSVrhuErQ+J27FLf3oAZ5oX4ujsWu9o0UkKaH63kBnMPtqFQXktlLBNKRsvJBG69THUebQniB/DyLeXT5oCOD4KFY+8MllC++EGMVmYTyI55XPOO8uJZwIHZ680PnkK3ExWM2hT6Aqz6CYbqomnpMJ7PZKaZGdvDvdfMyglVIWefsxQBQlBsjaAWR2cV5MCjmua+S8bqPywt5YhRGLbByUICmIfSDEdSe/3F0BgY915GjikcugBGPRusSHSEwrrCOtpSAOtQgOz+4gCyDR5EPSaDprCpCEmMT8aCqVxd2HrFH5rV4tqvGF3HOl1c0HhbH4M6NgJww9ehJgYpbntFF+GmgjcJgipuSPcq6ics6kkglm0S+hu+5JlKW4H/vOjGqXJ/gLrtdTjGczLRWY/xAYcjcHkbof7UFznoyvEFb+/nVJFDADAR3CLWBH97z/8xRCWY6HosQnTvzjTzg== X-Forefront-Antispam-Report: CIP:194.138.21.74; CTRY:DE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:hybrid.siemens.com; PTR:hybrid.siemens.com; CAT:NONE; SFS:(13230022)(4636009)(376002)(346002)(136003)(39860400002)(396003)(451199015)(36840700001)(46966006)(40470700004)(36756003)(186003)(5660300002)(54906003)(40480700001)(4326008)(316002)(47076005)(2616005)(16526019)(1076003)(110136005)(26005)(336012)(40460700003)(956004)(82960400001)(8936002)(41300700001)(36860700001)(2906002)(7636003)(6666004)(82740400003)(70586007)(86362001)(70206006)(8676002)(82310400005)(66899015)(478600001)(356005)(83380400001)(7596003); DIR:OUT; SFP:1101; X-OriginatorOrg: siemens.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2022 13:31:01.8259 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36e21dbf-039d-41ee-4a3f-08dabcd67c32 X-MS-Exchange-CrossTenant-Id: 38ae3bcd-9579-4fd4-adda-b42e1495d55a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=38ae3bcd-9579-4fd4-adda-b42e1495d55a; Ip=[194.138.21.74]; Helo=[hybrid.siemens.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR01FT054.eop-EUR01.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR10MB7328 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Benedikt Niedermayr Currently it is not possible to configure the WAIT0PINPOLARITY and WAIT1PINPOLARITY bits of the GPMC_CONFIG register directly via device tree properties. It is also not possible to use the same wait-pin for different cs-regions. While the current implementation may fullfill most usecases, it may not be sufficient for more complex setups (e.g. FPGA/ASIC interfaces), where more complex interfacing options where possible. For example interfacing an ASIC which offers multiple cs-regions but only one waitpin the current driver and dt-bindings are not sufficient. While using the same waitpin for different cs-regions worked for older kernels (4.14) the omap-gpmc.c driver refused to probe (-EBUSY) with newer kernels (>5.10). Changes since v1: * Rebase against recent 6.0.0-rc3 kernel * Updated eMail recipients list Changes since v2: * Remove the gpmc register configuration out of the gpiochip callbacks. In this case the memory interface configuration is not done via gpio bindings. * Some minor code fixes * Changed git commit descriptions Change since v3: * Use a uint32 dt-property instean a boolean one * If the dt-property is not set, then don't touch the GPMC_CONFIG register * Changed git commit descriptions Changes since v4: * Use checkpatch with "--strict" option * Moved wait-pin sanity checks to gpmc_read_settings_dt() * Always assign WAITPINPOLARITY_DEFAULT on error cases * Track waitpin allocation within gpmc for determine allocation origin Changes since v5: * Tracking of wait-pin allocations with polarity change detection * Introduced a new struct gpmc_waitpin * Add GPMC_* to global header definitions * Don't allow GPMC_WAITPINPOLARITY_DEFAULT when parsing dt-properties * Squashed wait-pin-polarity and shared-wait-pin patches, since they should not be separated Changes since v6: * Move wait-pin allocation into gpmc_probe() * Fix s/gpmc/GPMC/ in commit description * use ti,wait-pin-polarity instead of gpmc,wait-pin-polarity * Refactored if clause in gpmc_alloc_waitpin() * Revert values for GPMC_WAITPINPOLARITY_ACTIVE_LOW and GPMC_WAITPINPOLARITY_ACTIVE_HIGH. Use the exact same values which are written into the register. Changes since v7: * Renamed GPMC_WAITPINPOLARITY_DEFAULT to GPMC_WAITPINPOLARITY_INVALID * Call gpiochip_request_own_desc() only on first wait-pin allocation * Fixed use of old "gpmc,wait-pin-polarity" property. Changes since v8: * Fixed rebase against v6.0 * Add correct patch series version to each patch Benedikt Niedermayr (2): memory: omap-gpmc: wait pin additions dt-bindings: memory-controllers: gpmc-child: add wait-pin polarity .../memory-controllers/ti,gpmc-child.yaml | 7 + drivers/memory/omap-gpmc.c | 122 ++++++++++++++++-- include/linux/platform_data/gpmc-omap.h | 8 ++ 3 files changed, 124 insertions(+), 13 deletions(-) --- 2.25.1