From patchwork Mon Jul 13 11:01:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235375 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2725948ilg; Mon, 13 Jul 2020 04:01:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzrZzNKx89AVejIleAZkdh0vdzvI2va2xcXBE/jTiipSbSISVgsHAQhu7ZbljTo3HlGZ5BR X-Received: by 2002:a17:906:1394:: with SMTP id f20mr74574060ejc.114.1594638118395; Mon, 13 Jul 2020 04:01:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594638118; cv=none; d=google.com; s=arc-20160816; b=EhGu3XzpkDvBqSEVVqavmb0Aeq9s4xFminhoe1n+PB4KcOFiK3ZBC3BJE5audwhEbE aUrIp4fbmAJerD21csx3JfxaL/KZHkKWfEqWfZzVUfwsGe0UUezPsZIYlf6QAWzexfkt zaozvZ7cFzhJsB3626fZT7wub61GtOocXZfqkNQCkg97b/sFpa8qu5GF0xxO23zREMwF 92u5GQH8orraX4olMFyRf3RhsGivhw+WkBjVhQRZdxx8+Yu+jxu7qy+ApmhWNh6nWnBG bJ+F5JQhb4qtD8HIvKen3yUz/hkxpWl0Wo59CWC1kv2UkDDZ1fVZ+6v1ayvgv9JBqlqN XI6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=UEdxYmDQ26S+jeXjyhU2/1nqPRpaWvk6BoWO9iW6KTU=; b=i2VDPKL5ehT5Fdw8XOEWT1UHyltfE2wiWfOsYY0CHpguILnAsTIFwRtljG2cMU6UHA bIx/yAGOYel8ibPQTgG4e3ZqxRPhGYvfPZ+KnIW7A8YiliC5FH4HgilYF/M9wiVA1/zl u1kDE9qaS0bdiR25GBxWnrFe6saVjwWhFdYQrosQYCB8iGC+jNTUAvYVZ7jheQp7nlB8 k25kZ9Yu3t0Khcc8UC9bZ/8cQXe6/FzL96EPdIcKfAgKvSud0hVL+5yJRbCSPpEjfSB1 Xk+HEH7XENqjqzeIN91xBpu+lRp9LViQCnRcaG4aXOBp0fSaYqpl9REHx1/HY3D+/vzS SiAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=zBh8cnZ+; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id gj24si9129496ejb.139.2020.07.13.04.01.58; Mon, 13 Jul 2020 04:01:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=zBh8cnZ+; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729408AbgGMLB5 (ORCPT + 4 others); Mon, 13 Jul 2020 07:01:57 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:47964 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727035AbgGMLB5 (ORCPT ); Mon, 13 Jul 2020 07:01:57 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1kDQ093265; Mon, 13 Jul 2020 06:01:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594638106; bh=UEdxYmDQ26S+jeXjyhU2/1nqPRpaWvk6BoWO9iW6KTU=; h=From:To:CC:Subject:Date; b=zBh8cnZ+MeP3pOc9X5N/KgNaqJvB+KsZlhPZD9FP2+T2RY9S61xsVmRDmCCiKSx9I UM8UMSsFnzsLVySsSkT+S7OAc2ofDc/aaQ7fwOiHwz0n9aAdKmj6aLQmFwacEF+skn +ym1W5WJ+Eddlml8GpeS+cRZU9oS6f4YFqat63oM= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 06DB1kGn108271 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 13 Jul 2020 06:01:46 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 13 Jul 2020 06:01:46 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 13 Jul 2020 06:01:45 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06DB1gVa031460; Mon, 13 Jul 2020 06:01:42 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v7 00/14] Add PCIe support to TI's J721E SoC Date: Mon, 13 Jul 2020 16:31:27 +0530 Message-ID: <20200713110141.13156-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org TI's J721E SoC uses Cadence PCIe core to implement both RC mode and EP mode. The high level features are: *) Supports Legacy, MSI and MSI-X interrupt *) Supports upto GEN4 speed mode *) Supports SR-IOV *) Supports multiple physical function *) Ability to route all transactions via SMMU This patch series *) Add support in Cadence PCIe core to be used for TI's J721E SoC *) Add a driver for J721E PCIe wrapper v1 of the series can be found @ [1] v2 of the series can be found @ [2] v3 of the series can be found @ [5] v4 of the series can be found @ [6] v5 of the series can be found @ [7] v6 of the series can be found @ [8] Changes from v6: 1) Fixed bot found errors running 'make dt_binding_check' Changes from v5: 1) Added Reviewed-by: for PATCH #6 2) Protect writes to PCI_STATUS with spin_lock during raising interrupts in EP mode to reduce the time between read and write of RMW. Changes from v4: 1) Added Reviewed-by: & Acked-by: tags from RobH 2) Removed un-used accessors for pcie-cadence.h and removed having ops for read/write accessors 3) Updated cdns,cdns-pcie-host.yaml to remove "mem" from reg Changes from v3: 1) Changed the order of files in MAINTAINTERS file to fix Joe's comments 2) Fixed indentation and added Reviewed-by: Rob Herring 3) Cleaned up computing msix_tbl 4) Fixed RobH's comment on J721E driver Changes from v2: 1) Converting Cadence binding to YAML schema was done as a separate series [3] & [4]. [3] is merged and [4] is pending. 2) Included MSI-X support in this series 3) Added link down interrupt handling (only error message) 4) Rebased to latest 5.7-rc1 5) Adapted TI J721E binding to [3] & [4] Changes from v1: 1) Added DT schemas cdns-pcie-host.yaml, cdns-pcie-ep.yaml and cdns-pcie.yaml for Cadence PCIe core and included it in TI's PCIe DT schema. 2) Added cpu_addr_fixup() for Cadence Platform driver. 3) Fixed subject/description/renamed functions as commented by Andrew Murray. [1] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com [2] -> http://lore.kernel.org/r/20200106102058.19183-1-kishon@ti.com [3] -> http://lore.kernel.org/r/20200305103017.16706-1-kishon@ti.com [4] -> http://lore.kernel.org/r/20200417114322.31111-1-kishon@ti.com [5] -> http://lore.kernel.org/r/20200417125753.13021-1-kishon@ti.com [6] -> http://lore.kernel.org/r/20200506151429.12255-1-kishon@ti.com [7] -> http://lore.kernel.org/r/20200522033631.32574-1-kishon@ti.com [8] -> http://lore.kernel.org/r/20200708093018.28474-1-kishon@ti.com Alan Douglas (1): PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I (13): PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path linux/kernel.h: Add PTR_ALIGN_DOWN macro PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses PCI: cadence: Add support to start link and verify link status PCI: cadence: Allow pci_host_bridge to have custom pci_ops dt-bindings: PCI: cadence: Remove "mem" from reg binding PCI: cadence: Add new *ops* for CPU addr fixup PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC PCI: j721e: Add TI J721E PCIe driver misc: pci_endpoint_test: Add J721E in pci_device_id table MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe .../bindings/pci/cdns,cdns-pcie-host.yaml | 8 +- .../bindings/pci/ti,j721e-pci-ep.yaml | 94 ++++ .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++ MAINTAINERS | 4 +- drivers/misc/pci_endpoint_test.c | 9 + drivers/pci/controller/cadence/Kconfig | 23 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-j721e.c | 493 ++++++++++++++++++ .../pci/controller/cadence/pcie-cadence-ep.c | 129 ++++- .../controller/cadence/pcie-cadence-host.c | 59 ++- .../controller/cadence/pcie-cadence-plat.c | 13 + drivers/pci/controller/cadence/pcie-cadence.c | 8 +- drivers/pci/controller/cadence/pcie-cadence.h | 133 ++++- include/linux/kernel.h | 1 + 14 files changed, 1035 insertions(+), 53 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml create mode 100644 drivers/pci/controller/cadence/pci-j721e.c -- 2.17.1