| Message ID | 20190325093947.32633-1-kishon@ti.com |
|---|---|
| Headers | show |
| Series | Add support for PCIe RC and EP mode in TI's AM654 SoC | expand |
On Mon, Mar 25, 2019 at 03:09:33PM +0530, Kishon Vijay Abraham I wrote: > hook_fault_code is an ARM32 specific API for hooking into data abort. > Since pci-keystone.c will be used for AM65X platforms which is an > ARM64 platform, Hi Kishon, How is the problem plugged by the fault hook fixed on ARM64 ? Thanks, Lorenzo > allow hook_fault_code to be compiled only for ARM32. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c > index dfe54553d832..93296d434f40 100644 > --- a/drivers/pci/controller/dwc/pci-keystone.c > +++ b/drivers/pci/controller/dwc/pci-keystone.c > @@ -710,6 +710,7 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) > return ret; > } > > +#ifdef CONFIG_ARM > /* > * When a PCI device does not exist during config cycles, keystone host gets a > * bus error instead of returning 0xffffffff. This handler always returns 0 > @@ -729,6 +730,7 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, > > return 0; > } > +#endif > > static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) > { > @@ -778,12 +780,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) > if (ret < 0) > return ret; > > +#ifdef CONFIG_ARM > /* > * PCIe access errors that result into OCP errors are caught by ARM as > * "External aborts" > */ > hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, > "Asynchronous external abort"); > +#endif > > ks_pcie_start_link(pci); > dw_pcie_wait_for_link(pci); > -- > 2.17.1 >
Hi Lorenzo, On 11/04/19 8:33 PM, Lorenzo Pieralisi wrote: > On Mon, Mar 25, 2019 at 03:09:33PM +0530, Kishon Vijay Abraham I wrote: >> hook_fault_code is an ARM32 specific API for hooking into data abort. >> Since pci-keystone.c will be used for AM65X platforms which is an >> ARM64 platform, > > Hi Kishon, > > How is the problem plugged by the fault hook fixed on ARM64 ? At least in AM654 platform, I don't see a bus error when PCIe device is not connected but returns 0xffffffff. So there is no necessary for hook_fault_code in AM654 platform. Thanks Kishon > > Thanks, > Lorenzo > >> allow hook_fault_code to be compiled only for ARM32. >> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >> --- >> drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c >> index dfe54553d832..93296d434f40 100644 >> --- a/drivers/pci/controller/dwc/pci-keystone.c >> +++ b/drivers/pci/controller/dwc/pci-keystone.c >> @@ -710,6 +710,7 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) >> return ret; >> } >> >> +#ifdef CONFIG_ARM >> /* >> * When a PCI device does not exist during config cycles, keystone host gets a >> * bus error instead of returning 0xffffffff. This handler always returns 0 >> @@ -729,6 +730,7 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, >> >> return 0; >> } >> +#endif >> >> static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) >> { >> @@ -778,12 +780,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) >> if (ret < 0) >> return ret; >> >> +#ifdef CONFIG_ARM >> /* >> * PCIe access errors that result into OCP errors are caught by ARM as >> * "External aborts" >> */ >> hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, >> "Asynchronous external abort"); >> +#endif >> >> ks_pcie_start_link(pci); >> dw_pcie_wait_for_link(pci); >> -- >> 2.17.1 >>
On Mon, Mar 25, 2019 at 03:09:35PM +0530, Kishon Vijay Abraham I wrote: > Add PCIe RC support for AM654x Platforms in pci-keystone.c > +static int ks_pcie_am654_msi_host_init(struct pcie_port *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct device *dev = pci->dev; > + > + dev_vdbg(dev, "dummy function so that DW core doesn't configure MSI\n"); Drive-by nit: this is the first occurrence of dev_vdbg() in drivers/pci, and while dev_vdbg() might be useful somewhere, I'm not sure this is the place. It took me 10 minutes of archaeology to figure out what it is and how to use it. Apparently it does nothing at all unless you define VERBOSE_DEBUG, which can be set via Kconfig in a few cases: drivers/dma/Makefile:subdir-ccflags-$(CONFIG_DMADEVICES_VDEBUG) += -DVERBOSE_DEBUG drivers/usb/dwc2/Makefile:ccflags-$(CONFIG_USB_DWC2_VERBOSE) += -DVERBOSE_DEBUG drivers/usb/gadget/Makefile:subdir-ccflags-$(CONFIG_USB_GADGET_VERBOSE) += -DVERBOSE_DEBUG but is more commonly set by adding "#define VERBOSE_DEBUG" manually in a source file. Neither one applies here, so I don't think this actually does anything. Anyway, I suspect this particular message would make a lot of sense as a *comment*, but maybe not as a mysterious dev_vdbg() that never actually does anything. > + return 0; > +}
On Fri, Apr 12, 2019 at 04:48:36PM +0100, Lorenzo Pieralisi wrote: > On Mon, Mar 25, 2019 at 03:09:21PM +0530, Kishon Vijay Abraham I wrote: > > Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654 > > uses Synopsys core revision 4.90a and uses the same TI wrapper as used > > in keystone2 with certain modification. Hence AM654 will use the same > > pci wrapper driver pci-keystone.c > > > > This series was initially part of [1]. This series only includes patches > > that has to be merged via Lorenzo's tree. The PHY patches and dt patches > > will be sent separately. > > > > This series is created over keystone MSI cleanup series [2]. > > > > This series: > > *) Cleanup pci-keystone driver so that both RC mode and EP mode of > > AM654 can be supported > > *) Modify epc-core to support allocation of aligned buffers required for > > AM654 > > *) Fix ATU unroll identification > > *) Add support for both host mode and device mode in AM654 > > > > Changes from v2: > > *) Missed updating "Reviewed-by: Rob Herring <robh@kernel.org>" tags > > in the version that was sent to list. > > *) Add const qualifier to struct dw_pcie_ep_ops in pci-layerscape-ep.c > > > > Changes from v1: > > *) Support for legacy interrupt in AM654 is removed (see background here > > [3]) > > *) Allow of_pci_get_max_link_speed to be used by Endpoint controller > > driver > > *) Add support to set max-link-speed from DT in pci-keystone driver > > *) Update "Reviewed-by: Rob Herring <robh@kernel.org>" tags. > > > > [1] -> https://lore.kernel.org/patchwork/cover/989487/ > > [2] -> https://lkml.org/lkml/2019/3/21/193 > > [3] -> https://lkml.org/lkml/2019/3/19/235 > > > > Kishon Vijay Abraham I (26): > > PCI: keystone: Add start_link/stop_link dw_pcie_ops > > PCI: keystone: Cleanup error_irq configuration > > dt-bindings: PCI: keystone: Add "reg-names" binding information > > PCI: keystone: Perform host initialization in a single function > > PCI: keystone: Use platform_get_resource_byname to get memory > > resources > > PCI: keystone: Move initializations to appropriate places > > dt-bindings: PCI: Add dt-binding to configure PCIe mode > > PCI: keystone: Explicitly set the PCIe mode > > dt-bindings: PCI: Document "atu" reg-names > > PCI: dwc: Enable iATU unroll for endpoint too > > PCI: dwc: Fix ATU identification for designware version >= 4.80 > > PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 > > dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 > > PCI: keystone: Add support for PCIe RC in AM654x Platforms > > PCI: keystone: Invoke phy_reset API before enabling PHY > > PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint > > drivers > > PCI: keystone: Add support to set the max link speed from DT > > PCI: endpoint: Add support to allocate aligned buffers to be mapped in > > BARs > > PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops > > PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability > > offset > > PCI: dwc: Add callbacks for accessing dbi2 address space > > PCI: keystone: Add support for PCIe EP in AM654x Platforms > > PCI: designware-ep: Configure RESBAR to advertise the smallest size > > PCI: designware-ep: Use aligned ATU window for raising MSI interrupts > > misc: pci_endpoint_test: Add support to test PCI EP in AM654x > > misc: pci_endpoint_test: Fix test_reg_bar to be updated in > > pci_endpoint_test > > > > .../bindings/pci/designware-pcie.txt | 7 +- > > .../devicetree/bindings/pci/pci-keystone.txt | 14 +- > > drivers/misc/pci_endpoint_test.c | 18 + > > drivers/pci/Makefile | 2 +- > > drivers/pci/controller/dwc/Kconfig | 25 +- > > drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- > > drivers/pci/controller/dwc/pci-keystone.c | 577 +++++++++++++++--- > > .../pci/controller/dwc/pci-layerscape-ep.c | 2 +- > > drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- > > .../pci/controller/dwc/pcie-designware-ep.c | 55 +- > > .../pci/controller/dwc/pcie-designware-host.c | 19 - > > .../pci/controller/dwc/pcie-designware-plat.c | 2 +- > > drivers/pci/controller/dwc/pcie-designware.c | 52 ++ > > drivers/pci/controller/dwc/pcie-designware.h | 15 +- > > drivers/pci/endpoint/functions/pci-epf-test.c | 5 +- > > drivers/pci/endpoint/pci-epf-core.c | 10 +- > > drivers/pci/of.c | 44 +- > > include/linux/pci-epc.h | 2 + > > include/linux/pci-epf.h | 3 +- > > 19 files changed, 683 insertions(+), 173 deletions(-) > > Hi Kishon, > > I have applied the series, after rewriting the commit logs we > discussed, branch: pci/keystone, please have a look and let me know > if that's good to go. It all looks good to me; I responded to a few things I noticed while writing the notes for merging the branch. I don't think there were any must-fix things, but if you update the branch for any other reason, I'll happily remerge it (I remerge the "next" branch from scratch every time I add things anyway, so it's no work on my side). Bjorn
On Mon, Mar 25, 2019 at 03:09:43PM +0530, Kishon Vijay Abraham I wrote: > Add PCIe EP support for AM654x Platforms in pci-keystone.c > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > drivers/pci/controller/dwc/Kconfig | 23 +- > drivers/pci/controller/dwc/pci-keystone.c | 242 +++++++++++++++++++--- > 2 files changed, 236 insertions(+), 29 deletions(-) Hi Kishon, WARNING: DT compatible string "ti,am654-pcie-ep" appears un-documented -- check /work/sandbox/pci/Documentation/devicetree/bindings/ #301: FILE: drivers/pci/controller/dwc/pci-keystone.c:1179: + .compatible = "ti,am654-pcie-ep", I would like this warning to be fixed please on this patch. Thanks, Lorenzo > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > index d1d00833e0b3..b450ad2823a5 100644 > --- a/drivers/pci/controller/dwc/Kconfig > +++ b/drivers/pci/controller/dwc/Kconfig > @@ -105,14 +105,33 @@ config PCIE_SPEAR13XX > config PCI_KEYSTONE > bool "TI Keystone PCIe controller" > depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) > - depends on PCI_MSI_IRQ_DOMAIN > - select PCIE_DW_HOST > help > Say Y here if you want to enable PCI controller support on Keystone > SoCs. The PCI controller on Keystone is based on DesignWare hardware > and therefore the driver re-uses the DesignWare core functions to > implement the driver. > > +if PCI_KEYSTONE > + > +config PCI_KEYSTONE_HOST > + bool "PCI Keystone Host Mode" > + depends on PCI_MSI_IRQ_DOMAIN > + select PCIE_DW_HOST > + default y > + help > + Enables support for the PCIe controller in the Keystone SoC to work in > + host mode. > + > +config PCI_KEYSTONE_EP > + bool "PCI Keystone Endpoint Mode" > + depends on PCI_ENDPOINT > + select PCIE_DW_EP > + help > + Enables support for the PCIe controller in the Keystone SoC to work in > + endpoint mode. > + > +endif > + > config PCI_LAYERSCAPE > bool "Freescale Layerscape PCIe controller" > depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) > diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c > index 312fd0c49bbb..459485b0f65d 100644 > --- a/drivers/pci/controller/dwc/pci-keystone.c > +++ b/drivers/pci/controller/dwc/pci-keystone.c > @@ -52,6 +52,12 @@ > #define OB_ENABLEN BIT(0) > #define OB_WIN_SIZE 8 /* 8MB */ > > +#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) > +#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) > +#define PCIE_EP_IRQ_SET 0x64 > +#define PCIE_EP_IRQ_CLR 0x68 > +#define INT_ENABLE BIT(0) > + > /* IRQ register defines */ > #define IRQ_EOI 0x050 > > @@ -95,11 +101,16 @@ > #define KS_PCIE_SYSCLOCKOUTEN BIT(0) > > #define AM654_PCIE_DEV_TYPE_MASK 0x3 > +#define AM654_WIN_SIZE SZ_64K > + > +#define APP_ADDR_SPACE_0 (16 * SZ_1K) > > #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) > > struct ks_pcie_of_data { > + enum dw_pcie_device_mode mode; > const struct dw_pcie_host_ops *host_ops; > + const struct dw_pcie_ep_ops *ep_ops; > unsigned int version; > }; > > @@ -877,12 +888,139 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, > return 0; > } > > +static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base, > + u32 reg, size_t size) > +{ > + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); > + u32 val; > + > + ks_pcie_set_dbi_mode(ks_pcie); > + dw_pcie_read(base + reg, size, &val); > + ks_pcie_clear_dbi_mode(ks_pcie); > + return val; > +} > + > +static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, > + u32 reg, size_t size, u32 val) > +{ > + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); > + > + ks_pcie_set_dbi_mode(ks_pcie); > + dw_pcie_write(base + reg, size, val); > + ks_pcie_clear_dbi_mode(ks_pcie); > +} > + > static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { > .start_link = ks_pcie_start_link, > .stop_link = ks_pcie_stop_link, > .link_up = ks_pcie_link_up, > + .read_dbi2 = ks_pcie_am654_read_dbi2, > + .write_dbi2 = ks_pcie_am654_write_dbi2, > }; > > +static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > + int flags; > + > + ep->page_size = AM654_WIN_SIZE; > + flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; > + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); > + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); > +} > + > +static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) > +{ > + struct dw_pcie *pci = ks_pcie->pci; > + u8 int_pin; > + > + int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); > + if (int_pin == 0 || int_pin > 4) > + return; > + > + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), > + INT_ENABLE); > + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); > + mdelay(1); > + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); > + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), > + INT_ENABLE); > +} > + > +static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, > + enum pci_epc_irq_type type, > + u16 interrupt_num) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); > + > + switch (type) { > + case PCI_EPC_IRQ_LEGACY: > + ks_pcie_am654_raise_legacy_irq(ks_pcie); > + break; > + case PCI_EPC_IRQ_MSI: > + dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); > + break; > + default: > + dev_err(pci->dev, "UNKNOWN IRQ type\n"); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static const struct pci_epc_features ks_pcie_am654_epc_features = { > + .linkup_notifier = false, > + .msi_capable = true, > + .msix_capable = false, > + .reserved_bar = 1 << BAR_0 | 1 << BAR_1, > + .bar_fixed_64bit = 1 << BAR_0, > + .bar_fixed_size[2] = SZ_1M, > + .bar_fixed_size[3] = SZ_64K, > + .bar_fixed_size[4] = 256, > + .bar_fixed_size[5] = SZ_1M, > + .align = SZ_1M, > +}; > + > +static const struct pci_epc_features* > +ks_pcie_am654_get_features(struct dw_pcie_ep *ep) > +{ > + return &ks_pcie_am654_epc_features; > +} > + > +static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { > + .ep_init = ks_pcie_am654_ep_init, > + .raise_irq = ks_pcie_am654_raise_irq, > + .get_features = &ks_pcie_am654_get_features, > +}; > + > +static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie, > + struct platform_device *pdev) > +{ > + int ret; > + struct dw_pcie_ep *ep; > + struct resource *res; > + struct device *dev = &pdev->dev; > + struct dw_pcie *pci = ks_pcie->pci; > + > + ep = &pci->ep; > + > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); > + if (!res) > + return -EINVAL; > + > + ep->phys_base = res->start; > + ep->addr_size = resource_size(res); > + > + ret = dw_pcie_ep_init(ep); > + if (ret) { > + dev_err(dev, "failed to initialize endpoint\n"); > + return ret; > + } > + > + return 0; > +} > + > static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) > { > int num_lanes = ks_pcie->num_lanes; > @@ -950,7 +1088,8 @@ static int ks_pcie_set_mode(struct device *dev) > return 0; > } > > -static int ks_pcie_am654_set_mode(struct device *dev) > +static int ks_pcie_am654_set_mode(struct device *dev, > + enum dw_pcie_device_mode mode) > { > struct device_node *np = dev->of_node; > struct regmap *syscon; > @@ -963,7 +1102,18 @@ static int ks_pcie_am654_set_mode(struct device *dev) > return 0; > > mask = AM654_PCIE_DEV_TYPE_MASK; > - val = RC; > + > + switch (mode) { > + case DW_PCIE_RC_TYPE: > + val = RC; > + break; > + case DW_PCIE_EP_TYPE: > + val = EP; > + break; > + default: > + dev_err(dev, "INVALID device type %d\n", mode); > + return -EINVAL; > + } > > ret = regmap_update_bits(syscon, 0, mask, val); > if (ret) { > @@ -1006,6 +1156,13 @@ static const struct ks_pcie_of_data ks_pcie_rc_of_data = { > > static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { > .host_ops = &ks_pcie_am654_host_ops, > + .mode = DW_PCIE_RC_TYPE, > + .version = 0x490A, > +}; > + > +static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { > + .ep_ops = &ks_pcie_am654_ep_ops, > + .mode = DW_PCIE_EP_TYPE, > .version = 0x490A, > }; > > @@ -1019,16 +1176,22 @@ static const struct of_device_id ks_pcie_of_match[] = { > .data = &ks_pcie_am654_rc_of_data, > .compatible = "ti,am654-pcie-rc", > }, > + { > + .data = &ks_pcie_am654_ep_of_data, > + .compatible = "ti,am654-pcie-ep", > + }, > { }, > }; > > static int __init ks_pcie_probe(struct platform_device *pdev) > { > const struct dw_pcie_host_ops *host_ops; > + const struct dw_pcie_ep_ops *ep_ops; > struct device *dev = &pdev->dev; > struct device_node *np = dev->of_node; > const struct ks_pcie_of_data *data; > const struct of_device_id *match; > + enum dw_pcie_device_mode mode; > struct dw_pcie *pci; > struct keystone_pcie *ks_pcie; > struct device_link **link; > @@ -1053,6 +1216,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) > > version = data->version; > host_ops = data->host_ops; > + ep_ops = data->ep_ops; > + mode = data->mode; > > ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); > if (!ks_pcie) > @@ -1078,16 +1243,11 @@ static int __init ks_pcie_probe(struct platform_device *pdev) > ks_pcie->is_am6 = true; > > pci->dbi_base = base; > + pci->dbi_base2 = base; > pci->dev = dev; > pci->ops = &ks_pcie_dw_pcie_ops; > pci->version = version; > > - ret = of_property_read_u32(np, "num-viewport", &num_viewport); > - if (ret < 0) { > - dev_err(dev, "unable to read *num-viewport* property\n"); > - return ret; > - } > - > irq = platform_get_irq(pdev, 0); > if (irq < 0) { > dev_err(dev, "missing IRQ resource: %d\n", irq); > @@ -1136,7 +1296,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) > ks_pcie->pci = pci; > ks_pcie->link = link; > ks_pcie->num_lanes = num_lanes; > - ks_pcie->num_viewport = num_viewport; > ks_pcie->phy = phy; > > gpiod = devm_gpiod_get_optional(dev, "reset", > @@ -1172,7 +1331,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) > > pci->atu_base = atu_base; > > - ret = ks_pcie_am654_set_mode(dev); > + ret = ks_pcie_am654_set_mode(dev, mode); > if (ret < 0) > goto err_get_sync; > } else { > @@ -1181,29 +1340,58 @@ static int __init ks_pcie_probe(struct platform_device *pdev) > goto err_get_sync; > } > > - /* > - * "Power Sequencing and Reset Signal Timings" table in > - * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 > - * indicates PERST# should be deasserted after minimum of 100us > - * once REFCLK is stable. The REFCLK to the connector in RC > - * mode is selected while enabling the PHY. So deassert PERST# > - * after 100 us. > - */ > - if (gpiod) { > - usleep_range(100, 200); > - gpiod_set_value_cansleep(gpiod, 1); > - } > - > link_speed = of_pci_get_max_link_speed(np); > if (link_speed < 0) > link_speed = 2; > > ks_pcie_set_link_speed(pci, link_speed); > > - pci->pp.ops = host_ops; > - ret = ks_pcie_add_pcie_port(ks_pcie, pdev); > - if (ret < 0) > - goto err_get_sync; > + switch (mode) { > + case DW_PCIE_RC_TYPE: > + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { > + ret = -ENODEV; > + goto err_get_sync; > + } > + > + ret = of_property_read_u32(np, "num-viewport", &num_viewport); > + if (ret < 0) { > + dev_err(dev, "unable to read *num-viewport* property\n"); > + return ret; > + } > + > + /* > + * "Power Sequencing and Reset Signal Timings" table in > + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 > + * indicates PERST# should be deasserted after minimum of 100us > + * once REFCLK is stable. The REFCLK to the connector in RC > + * mode is selected while enabling the PHY. So deassert PERST# > + * after 100 us. > + */ > + if (gpiod) { > + usleep_range(100, 200); > + gpiod_set_value_cansleep(gpiod, 1); > + } > + > + ks_pcie->num_viewport = num_viewport; > + pci->pp.ops = host_ops; > + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); > + if (ret < 0) > + goto err_get_sync; > + break; > + case DW_PCIE_EP_TYPE: > + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { > + ret = -ENODEV; > + goto err_get_sync; > + } > + > + pci->ep.ops = ep_ops; > + ret = ks_pcie_add_pcie_ep(ks_pcie, pdev); > + if (ret < 0) > + goto err_get_sync; > + break; > + default: > + dev_err(dev, "INVALID device type %d\n", mode); > + } > > ks_pcie_enable_error_irq(ks_pcie); > > -- > 2.17.1 >
Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654 uses Synopsys core revision 4.90a and uses the same TI wrapper as used in keystone2 with certain modification. Hence AM654 will use the same pci wrapper driver pci-keystone.c This series was initially part of [1]. This series only includes patches that has to be merged via Lorenzo's tree. The PHY patches and dt patches will be sent separately. This series is created over keystone MSI cleanup series [2]. This series: *) Cleanup pci-keystone driver so that both RC mode and EP mode of AM654 can be supported *) Modify epc-core to support allocation of aligned buffers required for AM654 *) Fix ATU unroll identification *) Add support for both host mode and device mode in AM654 Changes from v2: *) Missed updating "Reviewed-by: Rob Herring <robh@kernel.org>" tags in the version that was sent to list. *) Add const qualifier to struct dw_pcie_ep_ops in pci-layerscape-ep.c Changes from v1: *) Support for legacy interrupt in AM654 is removed (see background here [3]) *) Allow of_pci_get_max_link_speed to be used by Endpoint controller driver *) Add support to set max-link-speed from DT in pci-keystone driver *) Update "Reviewed-by: Rob Herring <robh@kernel.org>" tags. [1] -> https://lore.kernel.org/patchwork/cover/989487/ [2] -> https://lkml.org/lkml/2019/3/21/193 [3] -> https://lkml.org/lkml/2019/3/19/235 Kishon Vijay Abraham I (26): PCI: keystone: Add start_link/stop_link dw_pcie_ops PCI: keystone: Cleanup error_irq configuration dt-bindings: PCI: keystone: Add "reg-names" binding information PCI: keystone: Perform host initialization in a single function PCI: keystone: Use platform_get_resource_byname to get memory resources PCI: keystone: Move initializations to appropriate places dt-bindings: PCI: Add dt-binding to configure PCIe mode PCI: keystone: Explicitly set the PCIe mode dt-bindings: PCI: Document "atu" reg-names PCI: dwc: Enable iATU unroll for endpoint too PCI: dwc: Fix ATU identification for designware version >= 4.80 PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 PCI: keystone: Add support for PCIe RC in AM654x Platforms PCI: keystone: Invoke phy_reset API before enabling PHY PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers PCI: keystone: Add support to set the max link speed from DT PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset PCI: dwc: Add callbacks for accessing dbi2 address space PCI: keystone: Add support for PCIe EP in AM654x Platforms PCI: designware-ep: Configure RESBAR to advertise the smallest size PCI: designware-ep: Use aligned ATU window for raising MSI interrupts misc: pci_endpoint_test: Add support to test PCI EP in AM654x misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test .../bindings/pci/designware-pcie.txt | 7 +- .../devicetree/bindings/pci/pci-keystone.txt | 14 +- drivers/misc/pci_endpoint_test.c | 18 + drivers/pci/Makefile | 2 +- drivers/pci/controller/dwc/Kconfig | 25 +- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-keystone.c | 577 +++++++++++++++--- .../pci/controller/dwc/pci-layerscape-ep.c | 2 +- drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- .../pci/controller/dwc/pcie-designware-ep.c | 55 +- .../pci/controller/dwc/pcie-designware-host.c | 19 - .../pci/controller/dwc/pcie-designware-plat.c | 2 +- drivers/pci/controller/dwc/pcie-designware.c | 52 ++ drivers/pci/controller/dwc/pcie-designware.h | 15 +- drivers/pci/endpoint/functions/pci-epf-test.c | 5 +- drivers/pci/endpoint/pci-epf-core.c | 10 +- drivers/pci/of.c | 44 +- include/linux/pci-epc.h | 2 + include/linux/pci-epf.h | 3 +- 19 files changed, 683 insertions(+), 173 deletions(-) -- 2.17.1